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Participant
Participant
242 Views
Registered: ‎04-07-2017

[Bug] Automatic variables make xsim of Vivado 2020.1 crash

While migrating our SystemVerilog designs to 2020.1, we encountered a big amount of issues being related with automatic variables in blocks.

I've picked the following example, where I could track the issue down to a small piece of code:

module fopen;
	function void foo(string filename);
		automatic integer fd = $fopen(filename, "r");
		$fclose(fd);
	endfunction

	initial foo("");
endmodule

The simulator then usually crashes with an error like this:

FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Time: 0 ps  Iteration: 0  Process: /fopen/Initial7_0
  File: /home/albert/git/fpga/tmp/fopen.sv

HDL Line: /home/albert/git/fpga/tmp/fopen.sv:3

This is just one example. In other examples, we could work around this bug by reordering the automatic declarations, or introducing new scopes (begin - end).

Unfortunately, the instability of its simulator makes 2020.1 practically unusable for us. Is there any fix already in progress, or some known work-around?

Possibly, this issues is related with https://forums.xilinx.com/t5/Simulation-and-Verification/BUG-Appending-to-a-queue-after-an-automatic-variable-declaration/m-p/1132292

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3 Replies
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Participant
Participant
229 Views
Registered: ‎04-07-2017

I just double checked the example I gave on other Vivado versions. Actually this is crashing 2018.2 & 2019.2.1 as well. Anyhow, the general issues with automatic variables seem to be especially happening on 2020.1.

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Xilinx Employee
Xilinx Employee
168 Views
Registered: ‎06-10-2020

This is Bug in simulator , i have created CR for this.

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Participant
Participant
89 Views
Registered: ‎04-07-2017

Thank you.

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