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Registered: ‎06-17-2020

Bug in RAMB36E1 Verilog template (vivado/2017.2)

Hi Team,

I want to report a bug in the RAMB36E1 Verilog template which I am using in one of my projects.
Vivado version that I am using is vivado/2017.2

in specify block Verilog system tasks for a bus are not written bitwise, they are written as follows 

$setuphold (posedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, ADDRARDADDR_delay);

$setuphold (posedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, ADDRARDADDR_delay);

here ADDRARDADDR is a 16bit bus while stimulating the output ADDRARDADDR_delay appears as follows

img1.PNG

According to me, this system task should be written bitwise as described below

$setuphold (posedge CLKARDCLK, posedge ADDRARDADDR[N], 0:0:0, 0:0:0, notifier_addra0, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, ADDRARDADDR_delay[N]);

$setuphold (posedge CLKARDCLK, negedge ADDRARDADDR[N], 0:0:0, 0:0:0, notifier_addra0, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, ADDRARDADDR_delay[N]);

here N signifies the bit number which ranges [0:15]
After making the above-mentioned changes in the Verilog file and running the simulations the correct results were achieved as shown in the below waveform 

img2.PNG

 

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