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Adventurer
Adventurer
9,047 Views
Registered: ‎09-27-2010

Bug in Vivado simulator?

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Hi, colleagues.

I've found strange behavior of vivado simulator and I've reduced the code until this behavior persists.

entity test is
  Port (
  Clock : in std_logic;
  Dev_Linked : in std_logic_vector(0 downto 0);
  Dev_on : out std_logic_vector(0 downto 0)
  );
end entity test;

architecture Behavioral of test is

    function FormInitR_CHCS 
        return std_logic_vector is
    variable R : std_logic_vector(1 downto 0) := (others => '0');
    begin
        R := (others => '0');
        for i in 0 to 0 loop
            R(i * 2) := '1';
            R(i * 2 + 1) := '0';
        end loop;
        return R;
    end function FormInitR_CHCS;
    
    signal R_CHCS : STD_LOGIC_VECTOR(1 downto 0):=FormInitR_CHCS;
    signal Dev_On_s : STD_LOGIC_VECTOR(0 downto 0);		

    
begin

	R_CHCS_proc : process (Clock) is
    begin
        if rising_edge(Clock) then
            for i in 0 to 0 loop
                R_CHCS(i * 2) <= '0';
            end loop;
        end if;
    end process R_CHCS_proc;


    R_CHCS4xip1 : for i in 0 to 0 generate
        R_CHCS(i * 2 + 1) <= Dev_Linked(i) when rising_edge(Clock);
    end generate R_CHCS4xip1;

	Device_control : process(Clock)						   
	begin
        if rising_edge(Clock) then
            for i in 0 to 0 loop	
                Dev_On(i) <= R_CHCS(i * 2+1);																	
            end loop;			   		
        end if;
	end process;	   

end Behavioral;

Synthesis of this gives us that:

buggysim.png

and it's perfectly OK but simulator gives unexpected 'X' values.

buggysimwave.png

 

Is it a bug or that's just me not understanding something important?

 

Vivado v2015.2 (64-bit)
SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015

Ilya
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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
16,864 Views
Registered: ‎10-24-2013

Re: Bug in Vivado simulator?

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Hi @siticompany
This looks to be multi driver issue.
•If you look at IEEE LRM 1800-2008, section 14.7.2, each process create a driver and in the same section you will find following“A driver always contains at least one transaction. The initial contents of a driver associated with a given signal are defined by the default value associated with the signal”
Which means that even if the signal assignment is under some condition, which is not going to be true during simulation, it will have a driver which is the default value of the signal.

 

In your case, line number 33 & 40 are treated as multi-drivers

 

Modify your code to bring those sections under one process to solve this issue.

 

begin

    R_CHCS_proc : process (Clock) is
    begin
        if rising_edge(Clock) then
            for i in 0 to 0 loop
                R_CHCS(i * 2) <= '0';
        R_CHCS(i * 2 + 1) <= Dev_Linked(i);-- when rising_edge(Clock);
            end loop;
        end if;
    end process R_CHCS_proc;


--    R_CHCS4xip1 : for i in 0 to 0 generate
--        R_CHCS(i * 2 + 1) <= Dev_Linked(i) when rising_edge(Clock);
--    end generate R_CHCS4xip1;

Thanks,Vijay
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7 Replies
Moderator
Moderator
9,017 Views
Registered: ‎04-17-2011

Re: Bug in Vivado simulator?

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Is the screenshot for Post-Synthesis simulation? Is behavioral simulation working properly?
Regards,
Debraj
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Adventurer
Adventurer
8,984 Views
Registered: ‎09-27-2010

Re: Bug in Vivado simulator?

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It is behavioral simulation.

Ilya
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Xilinx Employee
Xilinx Employee
8,974 Views
Registered: ‎10-24-2013

Re: Bug in Vivado simulator?

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Hi,
Looks to be issue with your design. Questa also gives the same output.
Can you write a testbench and see whats going wrong?
Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
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Xilinx Employee
Xilinx Employee
16,865 Views
Registered: ‎10-24-2013

Re: Bug in Vivado simulator?

Jump to solution

Hi @siticompany
This looks to be multi driver issue.
•If you look at IEEE LRM 1800-2008, section 14.7.2, each process create a driver and in the same section you will find following“A driver always contains at least one transaction. The initial contents of a driver associated with a given signal are defined by the default value associated with the signal”
Which means that even if the signal assignment is under some condition, which is not going to be true during simulation, it will have a driver which is the default value of the signal.

 

In your case, line number 33 & 40 are treated as multi-drivers

 

Modify your code to bring those sections under one process to solve this issue.

 

begin

    R_CHCS_proc : process (Clock) is
    begin
        if rising_edge(Clock) then
            for i in 0 to 0 loop
                R_CHCS(i * 2) <= '0';
        R_CHCS(i * 2 + 1) <= Dev_Linked(i);-- when rising_edge(Clock);
            end loop;
        end if;
    end process R_CHCS_proc;


--    R_CHCS4xip1 : for i in 0 to 0 generate
--        R_CHCS(i * 2 + 1) <= Dev_Linked(i) when rising_edge(Clock);
--    end generate R_CHCS4xip1;

Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

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Adventurer
Adventurer
8,949 Views
Registered: ‎09-27-2010

Re: Bug in Vivado simulator?

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I don't think so...

If that would be the case, removing unnecessary "for i in 0 to 0 loop" on lines 32 and 34 wouldn't change the result, but it does. In that case

 

	R_CHCS_proc : process (Clock) is
    begin
        if rising_edge(Clock) then
--            for i in 0 to 0 loop
                R_CHCS(0 * 2) <= '0';
--            end loop;
        end if;
    end process R_CHCS_proc;

we don't have 'x' values despite there is almost the same situation.

 

I think there is something with loops. May be they creates drivers for signals which doesn't realy should be affected by this "for" loop.

 

I've already worked around this issue by changing some initial values to 'U', but I want either to understand what is going on or to help you to find error if it is the case.

Ilya
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Xilinx Employee
Xilinx Employee
8,941 Views
Registered: ‎10-24-2013

Re: Bug in Vivado simulator?

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HI @siticompany

 

Did you try the modification I suggested? With that I dont see the unexpected X in the simulation.

Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
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Adventurer
Adventurer
8,933 Views
Registered: ‎09-27-2010

Re: Bug in Vivado simulator?

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Yes, I've tried. It helps as well as my way.

I just have doubts about reasons of such behaviour.

Thank you anyway.

Ilya
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