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Observer
Observer
433 Views
Registered: ‎05-10-2018

Bug with signal assignment outside case block

    logic [10:0] b;
logic [10:0] a; always_comb begin : sm_comb //State Machine Default Signal States a = 0; b = a; case(state_r)
SOME_STATE: begin
a = 1000;
b = a;
state = SOME_OTHER_STATE;
end ...

Above is an example of the code that causes the issue.

So lets say I have a signal' a' that I set to 0 by default outside the case block. I set signal b=a by default.

Theoretically, whenever a changes value, b=a, so 'b' should change value as well. So when a=1000, 'b' should also equal 1000.

However this is not what happens in simulation OR synthesis. In simulation, 'b' stays locked to whatever the default value of 'a' is! So if 'a' is set to 0 by default, 'b' always equals 0. If 'a' is set to 523 by default, 'b' always is equal to 523. Signal 'a' is changing values in the simulation, yet 'b' is always locked to the default of 'a'. Even if I set 'b' equal to a different value within one of the states, it does NOT change. 

In synthesis, 'b' does not get optimized away, but instead gets synthesized into logic via 'a' passing through LUTs and always producing the default value.

It gets weirder because this only happens if 'a' is set to a constant by default, and 'b' is set to 'a' by default. If I have a register, say

logic [10:0] some_reg;

And a=some_reg by default, 'b' will constantly match the value of 'a'. Which is the behavior I would expect.

Is this expected tool behavior?

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2 Replies
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Observer
Observer
419 Views
Registered: ‎05-10-2018

Re: Bug with signal assignment outside case block

It gets weirder:

    logic [10:0] b;
    logic [10:0] a;
    
    always_comb begin : sm_comb  
        //State Machine Default Signal States
        b = a;
        a = 0;
        case(state_r)
            SOME_STATE: begin
                a = 1000;
                state = SOME_OTHER_STATE;
            end 
            ...

If I just rearrange the default value, now 'b' is equal to 'a' delayed by a clock cycle in simulation.

This is an always_comb block...and this is the only assignment to 'b' in the source code...so how is 'b' being turned into a clocked register?

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Moderator
Moderator
293 Views
Registered: ‎09-15-2016

Re: Bug with signal assignment outside case block

Hi @dpikul ,

I have tried this at my end in Vivado 2019.1 with the below code, i see that b changes whenever there is a change in a.

always.JPG

Can you please try in Vivado 2019.1 and if you are still facing issues then can you please share the complete test case to check this issue at our end.

Thanks & Regards,
Sravanthi B
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