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Visitor
Visitor
5,770 Views
Registered: ‎05-01-2009

'CMPY_V2_1' is not defined

Hello,everyone.

 

    I have synthesised the cmult IP and added it to a verilog model. The process of synthesis is correct. But, when i simulated it in modelsim 6.3c, these error occured: vsim work.one2two # vsim work.one2two # ** Note: (vsim-3812) Design is being optimized... # ** Error: mult.v(85): Module 'CMPY_V2_1' is not defined. # Optimization failed # Error loading design

 

Did someone have this problem and solved it, please give me some help. Thank you! Kudos! Thanks!

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Xilinx Employee
Xilinx Employee
5,768 Views
Registered: ‎11-28-2007

Did you compile the simulation libraries (CoreGen in particular)? When you run vsim, did you include XILINXCORELIB in your library search path?

 

Cheers,

Jim

 

Cheers,
Jim
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Visitor
Visitor
5,746 Views
Registered: ‎05-01-2009

hello,Jim

 

     this problem have been solved. the reason is that the vhdl library not loaded when i turn on the modelsim from ISE. I added the vhdl library to the modelsim library again by manul. the problem is solved.

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