05-05-2009 07:47 AM
I have synthesised the cmult IP and added it to a verilog model. The process of synthesis is correct. But, when i simulated it in modelsim 6.3c, these error occured: vsim work.one2two # vsim work.one2two # ** Note: (vsim-3812) Design is being optimized... # ** Error: mult.v(85): Module 'CMPY_V2_1' is not defined. # Optimization failed # Error loading design
Did someone have this problem and solved it, please give me some help. Thank you! Kudos! Thanks!
05-05-2009 08:45 AM
Did you compile the simulation libraries (CoreGen in particular)? When you run vsim, did you include XILINXCORELIB in your library search path?
05-06-2009 05:55 AM
this problem have been solved. the reason is that the vhdl library not loaded when i turn on the modelsim from ISE. I added the vhdl library to the modelsim library again by manul. the problem is solved.