cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
gm300_syn
Visitor
Visitor
536 Views
Registered: ‎05-12-2019

Can I controll the clock jitter using clock vip?

Jump to solution

For clock VIP, PG 291 suggest clock vip can do something for clock jitter. actually, what that IP can do?

Can I add jitter to clock source to check the PLL stability?

 

not only jitter, feature section is listing several feature of - maybe clock VIP. Where I can read to find more details about this IP?

Features
• Sets interface into master/pass-through mode
• Starts/stops clock
• Sets/gets clock initial value
• Sets/gets clock period
• Sets/gets clock frequency
• Power ON/OFF clock jitter

0 Kudos
1 Solution

Accepted Solutions
yangc
Xilinx Employee
Xilinx Employee
517 Views
Registered: ‎02-27-2019

hi @gm300_syn ,

You can generate an example design and refer to its usage.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

3 Replies
yangc
Xilinx Employee
Xilinx Employee
518 Views
Registered: ‎02-27-2019

hi @gm300_syn ,

You can generate an example design and refer to its usage.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

gm300_syn
Visitor
Visitor
508 Views
Registered: ‎05-12-2019

Thanks, I will try.

0 Kudos
gm300_syn
Visitor
Visitor
424 Views
Registered: ‎05-12-2019

OK, I download the example and unpacked.

That package contains rich document about API to manipulate clk VIP.  and  SystemVerilog format function to enable VIP function.

Actually, without these function, VIP doesn't make sense. Everybody who want to use VIP need to use function in these SystemVerilog files.

 
Tags (1)
無題.png
0 Kudos