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Visitor
Visitor
384 Views
Registered: ‎05-12-2019

Can I controll the clock jitter using clock vip?

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For clock VIP, PG 291 suggest clock vip can do something for clock jitter. actually, what that IP can do?

Can I add jitter to clock source to check the PLL stability?

 

not only jitter, feature section is listing several feature of - maybe clock VIP. Where I can read to find more details about this IP?

Features
• Sets interface into master/pass-through mode
• Starts/stops clock
• Sets/gets clock initial value
• Sets/gets clock period
• Sets/gets clock frequency
• Power ON/OFF clock jitter

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Xilinx Employee
Xilinx Employee
365 Views
Registered: ‎02-27-2019

hi @gm300_syn ,

You can generate an example design and refer to its usage.

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Xilinx Employee
Xilinx Employee
366 Views
Registered: ‎02-27-2019

hi @gm300_syn ,

You can generate an example design and refer to its usage.

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Visitor
Visitor
356 Views
Registered: ‎05-12-2019

Thanks, I will try.

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Visitor
Visitor
272 Views
Registered: ‎05-12-2019

OK, I download the example and unpacked.

That package contains rich document about API to manipulate clk VIP.  and  SystemVerilog format function to enable VIP function.

Actually, without these function, VIP doesn't make sense. Everybody who want to use VIP need to use function in these SystemVerilog files.

 
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