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Anonymous
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Can ISE simulator run the simulation of the Endpoint Block Plus for PCI Express?

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Hi,

 

Can ISE simulator run the simulation of the Endpoint Block Plus for PCI Express?

There are three ways, vcs, ncsim and mti, in user guide(UG341), but no mentioning ISE simulator.

 

Thanks,

Hermes

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Xilinx Employee
Xilinx Employee
21,159 Views
Registered: ‎09-14-2007

Hi Manu,

 

I have attached a script that works for the device family you specified. I created it for Linux, although these are standard commands so it should work on Windows as well. Just ensure you change the $XILINX/veriilog/src/glbl.v to %XILINX%\verilog\src\glbl.v.

 

You will also see these messages about bad trailing charachters, although you can safely ignore this and it is same as what you would see with the other simulators as well.

 

The main changes are :

 

1. You will need have a script that uses ISim commands - simulate_isim.csh

2. You will need to modify some of the .f files as ISim does not support comments and calling one .f from another .f file. I have filed change requests to add support for this in ISim.

 

Please note - The Xilinx PCIe team does not officially support ISim and this is why you may not get support via the regular support channels.

 

Thanks

Duth

 

Message Edited by duthv on 10-28-2009 01:49 PM

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Xilinx Employee
Xilinx Employee
16,810 Views
Registered: ‎09-14-2007

Hi Hermes,

 

Yes the simulation does work, although it is not officially supported by the PCIe team and this is why you dont see a script for it.

 

This is significantly easier to do with the 11.2 and if you can clarify which PCIe core you are using (V5, V6, S6), I can provide a script that should get you up and running.

 

Thanks

Duth

 

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Observer
Observer
16,524 Views
Registered: ‎11-21-2007

Hi,

 

I have been trying to simulate the PCIe core for V5 in ISIM for the last 2 days and got into quite a mess.

Still no simulation is running.

I am targetting a Virtex-5 SX50T and I, as well as others, would be extremely grateful to get a script to run the smiulation for version 1.12 of the core in ISE 11.3.

Thanks,

Regards,

Manu

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Xilinx Employee
Xilinx Employee
21,160 Views
Registered: ‎09-14-2007

Hi Manu,

 

I have attached a script that works for the device family you specified. I created it for Linux, although these are standard commands so it should work on Windows as well. Just ensure you change the $XILINX/veriilog/src/glbl.v to %XILINX%\verilog\src\glbl.v.

 

You will also see these messages about bad trailing charachters, although you can safely ignore this and it is same as what you would see with the other simulators as well.

 

The main changes are :

 

1. You will need have a script that uses ISim commands - simulate_isim.csh

2. You will need to modify some of the .f files as ISim does not support comments and calling one .f from another .f file. I have filed change requests to add support for this in ISim.

 

Please note - The Xilinx PCIe team does not officially support ISim and this is why you may not get support via the regular support channels.

 

Thanks

Duth

 

Message Edited by duthv on 10-28-2009 01:49 PM

View solution in original post

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Observer
Observer
16,502 Views
Registered: ‎11-21-2007

Hello Duth,

 

Thank you for your help.

I am a fairly new user of ISIM but I have experience in simulation.

The fact is that I cannot find in the ISIM documentation how to run your scripts using command line.

I used the ISE GUI to run the command file simulate_isim_gui.csh, after adding all the source files and correcting `includes issues with them.

but I end up with the same error as without the command file:

 

ERROR:HDLCompiler:559 - "N:/L.57/rtf/verilog/src/unisims/PCIE_2_0.v" Line 2957: Could not find module/primitive <B_PCIE_2_0>.
ERROR:HDLCompiler:559 - "N:/L.57/rtf/verilog/src/unisims/GTXE1.v" Line 2500: Could not find module/primitive <B_GTXE1>.
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed

 

I am not sure if it is just me not being able to find the way to run your script properly, or if the script is not used.

Well, I installed on another machine ISE11.2 and the simulation runs very using ISIM, I'm woried I have hit a bug in the libraries.

 

Thanks,

Regards,

Manu

 

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Xilinx Employee
Xilinx Employee
16,490 Views
Registered: ‎09-14-2007

Hi Manu,

 

To run the script, you just need to open a command prompt window and execute the script.

 

Doing this inside Proj Nav is a little more tricky and you wont be able to run this script directly inside the ISE GUI Tcl console, as this is intended to run directly in the OS command prompt. If you would like to convert the sample design to PN, then I would recommend that you open a case with Xilnx Technical Support as there is some work involved to get this to work in PN. 

 

http://www.xilinx.com/support/techsup/tappinfo.htm

 

Thanks

Duth

 

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Visitor
Visitor
16,433 Views
Registered: ‎11-03-2009

I had the same issue (missing those exact modules), except that I am using Modelsim PE 6.5c for simulation. 

 

I am working with ISE 11.3, and the PCIe V5 embedded core version 1.12. 

 

To solve the issue, I needed to manually locate the source files located within the Xilinx ISE install directory, and compile them into the appropriate library (ie "unisims_ver") within my ModelSim environment. 

 

Depending on your installation structure, it may look like this:

 

"$XILINX\verilog\src\unisims\GTXE1.v"

"$XILINX\verilog\src\unisims\PCIE_2_0.v"

 

 

I had previously performed a full simulation library compilation using the ISE 11.3 GUI/wizard, but apparently it missed some files.

 

Once you locate these files, you may then need to add and compile additional libraries in the "secureip" folder, you may find that now a module named "B_PCIE_2_0" is missing. 

 

In the secureip library, you should have all of the following added:

 

 B_PCIE_A1

 PCIE_2_0_WRAP

 PCIE_A1_WRAP

 PCIE_INTERNAL_1_1_SWIFT

 

Depending again on your installation and choice of simulator, the path to the files may look like this.

$XILINX\secureip\mti.... 

 

I am not sure which one contains the B_PCIE_2_0 module, but adding all of these fixed my sim. 

 

YMMV with other simulators. :)

 

-Scott

 

 

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Xilinx Employee
Xilinx Employee
16,422 Views
Registered: ‎09-14-2007

Hi Scott,

 

If you were using Compxlib (Compilation Wizard) to compile your simulation libraries, then you would not need to do these additional steps.

 

If you had to do these additonal steps then something else could be the problem, as complib should be  doing this for you already. Do note you should pick the correct device family when you run compxlib or it will not compile the correct SecureIP blocks for you.

 

More information on Compxlib can be found in the Command Line Tools Reference Guide :

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/devref.pdf

 

Chapter 26.

 

Thanks

Duth

 

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Visitor
Visitor
16,409 Views
Registered: ‎11-03-2009

I did use compxlib (GUI, not command line), I selected all devices/familes as well. 

 

I recently did a fresh installation of both Modelsim PE 6.5c and ISE 11.1 -> 11.2 -> 11.3 patches, then ran compxlib.....yet those files were still missing. 

 

I'll have a look at the link, thanks for posting it.

 

-Scott

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Xilinx Employee
Xilinx Employee
16,402 Views
Registered: ‎09-14-2007

Hi Scott,

 

Would it be possible for you to open a Case with Xilinx Support on this? I have done this multiple times and not seen a problem.

 

Something odd is going on here.

 

Thanks

Duth

 

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14,654 Views
Registered: ‎02-25-2010

Hi -- I am seeing the same problem:

 

ERROR:HDLCompiler:559 - "/build/xfndry10/L.68/rtf/verilog/src/unisims/PCIE_2_0.v" Line 2957: Could not find module/primitive <B_PCIE_2_0>.
ERROR:HDLCompiler:559 - "/build/xfndry10/L.68/rtf/verilog/src/unisims/GTXE1.v" Line 2515: Could not find module/primitive <B_GTXE1>.

 

Running w/ ISE (ISIM) 11.4 & PCIe Endpoint Block Plus v1.13.

 

Is there a known solution?

 

  Thanks,

   Daniel

 

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Xilinx Employee
Xilinx Employee
14,647 Views
Registered: ‎09-14-2007

Hi,

 

This is a known issue with the flow in project navigator. The problem had to do with the fact that the PCIe Endpoint Block Plus V1.13 uses V6 models for testbench and this is why ISim is not able to find it.

 

There is a  way to work around this problem.

 

If you right click on "simulate behavioral model" and select properties then under other compiler options, enter -L secureip

 

This should resolve the problem you are running into.

 

Thanks

Duth

 

Highlighted
14,644 Views
Registered: ‎02-25-2010

Thanks!  That fixes the problem.

 

-Daniel

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Visitor
Visitor
13,607 Views
Registered: ‎01-27-2011

Hi

I used the Cadence ISU.

 

It's issued "ncelab: *E,CUVMUR (/home/pclet/ISE11.5/ISE/verilog/src/unisims/PCIE_2_0.v,3195|18): instance 'test.PCIE@xilinx_pcie_2_0_rport_v6<module>.rport@pcie_2_0_rport_v6<module>.pcie_2_0_i@pcie_2_0_v6_rp<module>.pcie_block_i@PCIE_2_0<module>.B_PCIE_2_0_INST' of design unit 'B_PCIE_2_0' is unresolved in 'unisims.PCIE_2_0:v'."

 

I don't find unit "B_PCIE_2_0".

What I do?

 

Thanks

Michael

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Xilinx Employee
Xilinx Employee
13,593 Views
Registered: ‎09-14-2007

Hi,

 

From the error message it looks like you may not have compiled the libraries for Xilinx libraries as yet.

 

Please ensure that you are following Appendix B from the Synthesis and Simulation Design Guide:

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/sim.pdf

 

Thanks

Duth

 

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Anonymous
Not applicable
13,579 Views

Hi Duth,

 

Thank you for your help.

 

I have another problem.

"pci_exp_usrapp_rx.vhd" in PCI Express dsport files is issued following errors.

Why do it issue?

 

Thanks

Michael

 

======== Errors ====================================

constant COMPLETER_ID_CFG : std_logic_vector(15 downto 0) := X"01A0";
                                                                      |
ncvhdl_p: *E,EXPBEG (../PCIe_Ref_Design/v11_5/endpoint_blk_plus_v1_13/simulation/dsport/pci_exp_usrapp_rx.vhd,117|70): expecting the reserved word 'BEGIN' [1.2].
shared variable frame_store_rx         : BYTE_ARRAY;
       |
ncvhdl_p: *E,UNKCCS (../PCIe_Ref_Design/v11_5/endpoint_blk_plus_v1_13/simulation/dsport/pci_exp_usrapp_rx.vhd,121|7): unknown concurrent statement [9].
shared variable frame_store_rx_idx     : INTEGER;
       |
ncvhdl_p: *E,UNKCCS (../PCIe_Ref_Design/v11_5/endpoint_blk_plus_v1_13/simulation/dsport/pci_exp_usrapp_rx.vhd,122|7): unknown concurrent statement [9].
shared variable next_trn_rx_timeout    : INTEGER;
       |
ncvhdl_p: *E,UNKCCS (../PCIe_Ref_Design/v11_5/endpoint_blk_plus_v1_13/simulation/dsport/pci_exp_usrapp_rx.vhd,123|7): unknown concurrent statement [9].
shared variable next_trn_rx_timeout    : INTEGER;
                                                  |
ncvhdl_p: *E,EXPEND (../PCIe_Ref_Design/v11_5/endpoint_blk_plus_v1_13/simulation/dsport/pci_exp_usrapp_rx.vhd,123|50): expecting the reserved word 'END' [1.2].
signal trn_rdst_rdy_n_c       : std_logic;
                      |
ncvhdl_p: *E,ARCNMM (../PCIe_Ref_Design/v11_5/endpoint_blk_plus_v1_13/simulation/dsport/pci_exp_usrapp_rx.vhd,125|22): architecture body identifier mismatch (RTL/TRN_RDST_RDY_N_C) [1.2].
signal trn_rdst_rdy_n_c       : std_logic;
                        |
ncvhdl_p: *E,EXPSMI (../PCIe_Ref_Design/v11_5/endpoint_blk_plus_v1_13/simulation/dsport/pci_exp_usrapp_rx.vhd,125|24): expecting a semicolon (';') [1.2].
signal trn_rdst_rdy_n_c       : std_logic;
                                        |
ncvhdl_p: *E,ARCNMM (../PCIe_Ref_Design/v11_5/endpoint_blk_plus_v1_13/simulation/dsport/pci_exp_usrapp_rx.vhd,125|40): architecture body identifier mismatch (RTL/STD_LOGIC) [1.2].
signal trn_rnp_ok_n_c         : std_logic;
|
ncvhdl_p: *E,EXPACE (../PCIe_Ref_Design/v11_5/endpoint_blk_plus_v1_13/simulation/dsport/pci_exp_usrapp_rx.vhd,126|0): expecting a library unit [11.1].
end; -- pci_exp_usrapp_rx
ncvhdl_p: *E,UXPEOF (../PCIe_Ref_Design/v11_5/endpoint_blk_plus_v1_13/simulation/dsport/pci_exp_usrapp_rx.vhd,875): unexpected end of file.
        errors: 10, warnings: 0

 

 

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Xilinx Employee
Xilinx Employee
13,561 Views
Registered: ‎09-14-2007

Hi,

 

You need to tell the simualtor to use the VHDL 93 compiler, so try ncvhdl with the -v93 switch.

 

Also if you are just running the demo design, you can run the simulate_nc.csh script in the simulation/functional folder as well.

 

Thanks

Duth

 

 

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Anonymous
Not applicable
13,556 Views

Hi Duth,

 

Thank you for your help.

It's solved

 

Thanks

Michael.

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Newbie
Newbie
12,736 Views
Registered: ‎10-25-2011

Thank!!!!

Simulation OK.

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Visitor
Visitor
1,938 Views
Registered: ‎01-04-2018

Old post, I know. But does anyone still have the script provided by Duth? I am trying to get the wrapper example working in ISIM. 

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