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yjgao
Explorer
Explorer
10,797 Views
Registered: ‎07-24-2008

Can ISE13.1 support System Verilog for design and verification?

Hi all,

 

       Can ISE13.1 support System Verilog for design and verification?

 

Thanks.

Best Regards.

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13 Replies
duthv
Xilinx Employee
Xilinx Employee
10,782 Views
Registered: ‎09-14-2007

Hi,

 

SystemVerilog support is planned as part of our 14.1 release in CY 2012.

 

ISim will add support in phases, where we will initially support the SystemVerilog for Design constructs and then we will phase in the support for SystemVerilog for Verification.

 

Thanks

Duth

 

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mychalhall
Visitor
Visitor
10,383 Views
Registered: ‎07-14-2011

Duth,

 

What makes this any different than 3 years ago when a full production release was promised in 12.1?

http://forums.xilinx.com/t5/Archived-ISE-issues/I-hope-Systemverilog-will-be-supported-soon/m-p/21415/highlight/false

 

I've been hearing the same from our FAE saying that this will be supported "soon" for the past 4-5 years.  At least there are alternatives to Xilinx...

 

Message for the OP is don't believe ANYONE until you actually see it work.

 

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pmeyeratdatest
Visitor
Visitor
10,284 Views
Registered: ‎01-19-2010

Duth:

 

Could I please ask Xilinx to publish a commited roadmap for SystemVerilog support.  My primary interest is in SystemVerilog in design (ie XST/ISE HDL parser) as we are using a 3rd party SystemVerilog simulator. 

 

My thanks!

 

Peter

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goalyoung
Observer
Observer
9,819 Views
Registered: ‎11-20-2007

14.1?

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rcingham
Teacher
Teacher
9,813 Views
Registered: ‎09-09-2010

14.1 = 13.4 + 0.7

;-)

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"If it don't work in simulation, it won't work on the board."
tpduke
Newbie
Newbie
9,019 Views
Registered: ‎09-25-2012

Now that the latest ISE release is 14.2, is System Verilog supported for synthesis?

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graces
Moderator
Moderator
9,005 Views
Registered: ‎07-16-2008

System Verilog will not be supported in ISE releases. We'll add support in Vivado.

The current 2012.2 Vivado Simulator doesn't support SV yet.

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stmartin81
Adventurer
Adventurer
6,886 Views
Registered: ‎12-09-2010

Where can I get an overview which languages and which revisions of the languages are supported for synthesis and simulation? I've searched for SystemVerilog support in Vivado and this thread was the best overview of the current state I was able to find.

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stmartin81
Adventurer
Adventurer
6,881 Views
Registered: ‎12-09-2010

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vemulad
Xilinx Employee
Xilinx Employee
3,268 Views
Registered: ‎09-20-2012

Hi, 

 

Vivado synthesis supports System verilog. Please refer to chapter-3 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug901-vivado-synthesis.pdf for details on supported constructs.

 

Thanks,

Deepika.

Thanks,
Deepika.
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debrajr
Moderator
Moderator
3,258 Views
Registered: ‎04-17-2011

System Verilog is supported in Vivado 2014.1 and the listed constructs are present in document: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug900-vivado-logic-simulation.pdf.

As its a beta version you may see issues and it would be great if you can post them as soon as you see it.

Regards,
Debraj
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stmartin81
Adventurer
Adventurer
3,254 Views
Registered: ‎12-09-2010

Nice! Thanks for the update!

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debrajr
Moderator
Moderator
3,245 Views
Registered: ‎04-17-2011

Welcome!

If you have sometime feel free to chech this discussion

http://forums.xilinx.com/t5/Simulation-and-Verification/Do-you-use-SystemVerilog-DPI/td-p/459256

Regards,
Debraj
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