03-08-2011 06:53 PM
Can ISE13.1 support System Verilog for design and verification?
03-09-2011 08:02 AM
SystemVerilog support is planned as part of our 14.1 release in CY 2012.
ISim will add support in phases, where we will initially support the SystemVerilog for Design constructs and then we will phase in the support for SystemVerilog for Verification.
07-29-2011 05:40 PM
What makes this any different than 3 years ago when a full production release was promised in 12.1?
I've been hearing the same from our FAE saying that this will be supported "soon" for the past 4-5 years. At least there are alternatives to Xilinx...
Message for the OP is don't believe ANYONE until you actually see it work.
08-31-2011 08:51 AM
Could I please ask Xilinx to publish a commited roadmap for SystemVerilog support. My primary interest is in SystemVerilog in design (ie XST/ISE HDL parser) as we are using a 3rd party SystemVerilog simulator.
09-26-2012 12:03 AM
System Verilog will not be supported in ISE releases. We'll add support in Vivado.
The current 2012.2 Vivado Simulator doesn't support SV yet.
05-21-2014 02:46 AM
Where can I get an overview which languages and which revisions of the languages are supported for synthesis and simulation? I've searched for SystemVerilog support in Vivado and this thread was the best overview of the current state I was able to find.
05-21-2014 02:50 AM
05-21-2014 03:03 AM - edited 05-21-2014 03:04 AM
Vivado synthesis supports System verilog. Please refer to chapter-3 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug901-vivado-synthesis.pdf for details on supported constructs.
05-21-2014 11:27 PM
05-22-2014 11:33 PM
If you have sometime feel free to chech this discussion