03-02-2019 05:17 AM
The first image is my fifo and I marked the place I wanted to see. The second image is xilinx ip fifo. but I couldn't see FIFO memory content. Is there a way do this?
03-03-2019 08:38 PM
No. We dont have provision to check the FIFO content.
May i know the background of this query ? Are you seeing any abiguity with FIFO behaviour.
03-04-2019 12:11 AM
You may change elaboration option -debug_level from 'typical' to 'all' to enable more objects within IP.
How the memory element signal is displayed depends on how it is declared in IP models.
03-04-2019 01:40 AM - edited 03-04-2019 02:28 AM
The second image is xilinx ip fifo. but I couldn't see FIFO memory content. Is there a way do this?
If you have the correct write and read logic on both sides of the FIFO, then for every wr_clk if the we_en is HIGH then data would be written to the FIFO. Then if the rd_en is working and rd_clk is supplied, then you should be seeing the data which you have written, dout.
Thats an alternative and time consuming way to see the contents.