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martoni
Observer
Observer
4,628 Views
Registered: ‎02-20-2009

Can't do a post-routing simulation of dsp48a

Hello,

 

I instantiated dsp48a in a Spartan3a DSP and I synthetize it with success. The behavioural simulation work fine but post-place&route simulation fail with error:

 

 ERROR: Can not find hierarchical name dsp48_test.

 

I instanciated dsp48a in VHDL with following code:

 

 

    -- dsp48a: dsp function block
   --         spartan-3a dsp
   -- xilinx hdl language template, version 10.1.3
   dsp48_test : dsp48a
   generic map (
      a0reg => 1,          -- enable=1/disable=0 first stage a input pipeline register
      a1reg => 0,          -- enable=1/disable=0 second stage a input pipeline register
      b0reg => 1,          -- enable=1/disable=0 first stage b input pipeline register
      b1reg => 1,          -- enable=1/disable=0 second stage a input pipeline register
      carryinreg => 0,     -- enable=1/disable=0 first stage a input pipeline register
      carryinsel => "OPMODE5",  -- specify carry-in source, "carryin" or "opmode5"
      creg => 0,           -- enable=1/disable=0 c input pipeline register
      dreg => 0,           -- enable=1/disable=0 d pre-adder input pipeline register
      mreg => 1,           -- enable=1/disable=0 m pipeline register
      opmodereg => 0,      -- enable=1/disable=0 opmode input pipeline register
      preg => 1,           -- enable=1/disable=0 p output pipeline register
      rsttype => "ASYNC") -- specify reset type, "sync" or "async"
   port map (
      bcout => open,  -- 18-bit b port cascade output
      carryout => open, -- 1-bit carry output
      p => pout_3,          -- 48-bit output
      pcout => open,  -- 48-bit cascade output
      a => pain_3,          -- 18-bit a data input
      b => bcin_3,          -- 18-bit b data input (can be connected to fabric or bcout of adjacent dsp48a)
      c => (others => '0'),          -- 48-bit c data input
      carryin => '0', -- 1-bit carry input signal
      cea => '1',      -- 1-bit active high clock enable input for a input registers
      ceb => '1',      -- 1-bit active high clock enable input for b input registers
      cec => '0',      -- 1-bit active high clock enable input for c input registers
      cecarryin => '0', -- 1-bit active high clock enable input for carryin registers
      ced => '0',      -- 1-bit active high clock enable input for d input registers
      cem => '1',      -- 1-bit active high clock enable input for multiplier registers
      ceopmode => '0', -- 1-bit active high clock enable input for opmode registers
      cep => '1',       -- 1-bit active high clock enable input for p output registers
      clk => clk_i,       -- clock input
      d => (others => '0'),           -- 18-bit b pre-adder data input
      opmode => x"05", -- 8-bit operation mode input
      pcin => pcin_3,     -- 48-bit p cascade input
      rsta => reset_i,     -- 1-bit reset input for a input pipeline registers
      rstb => reset_i,     -- 1-bit reset input for b input pipeline registers
      rstc => reset_i,     -- 1-bit reset input for c input pipeline registers
      rstcarryin => reset_i, -- 1-bit reset input for carryin input pipeline registers
      rstd =>       reset_i,     -- 1-bit reset input for d input pipeline registers
      rstm =>       reset_i, -- 1-bit reset input for m pipeline registers
      rstopmode =>  reset_i, -- 1-bit reset input for opmode input pipeline registers
      rstp =>       reset_i  -- 1-bit reset input for p pipeline registers
);

 

 

Thanks

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2 Replies
edv
Xilinx Employee
Xilinx Employee
4,613 Views
Registered: ‎08-15-2007

martoni,

 

A Post-Route simulation should not simulate against your HDL code, but rather, the simulation model generated by NetGen from the implemented netlist (.ncd).  As such, the reason you are encountering this error is because the simulation flow is incorrect.

 

Are you launching the Post-Route simulation from Project Navigator?   If so, are you selecting "Simulate Post-Place and Route Simulation Model" while highlighting your testbench?  When you do this, right under the testbench, you should see only one submodule which, by default, should be populated by a file called <your top level entity name>_timesim.vhd.  Do you see anything different?

 

 

Eddie
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ticktack
Explorer
Explorer
4,588 Views
Registered: ‎08-14-2007

Hello, When you instantiate the DSP48a, did you uncomment following lines?

 

Library UNISIM;

use UNISIM.vcomponents.all;

 

 

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