09-27-2018 11:45 PM
I used a lot of ISERDES and OSERDES in a Virtex Ultrascale+ device in my test design. I made a simple test project using Vivado2018.2 and tried to run timing simulation. The project could generate the bitstream and did functional simulation successfully, but always failed when doing timing simulation(post sythesis and pos implementation). Below is the error gave by Vivado.
In elaborate.log in SIM:
Completed static elaboration
ERROR: [XSIM 43-3221] (SdfError)Error while parsing sdf file "lvds_top_time_impl.sdf" Line 24874: syntax error, unexpected IOPATH, expecting $end.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
I don't know whether the .sdf file has syntax error or there is any mistake in my design. By the way, the same design coule do timing simulation if I using a Ultrascale(not Ultrascale+) device.
Attachments is the project and the lvds_top_time_impl.sdf.
09-28-2018 02:24 PM - edited 09-28-2018 02:24 PM
Vivado v2018.2 seems to have problems doing timing simulations. Please see the following posts: