11-17-2016 09:17 AM
I am trying to load a block RAM with data in my design in Vivado.
I am using Vivado 16.2. I add a block memory in the block design tools. When I try to customize the memory , the "Load Init File " button is greyed out and I cannot add a file to setup the memory as I wish.
I tried using tcl or directly editing properties :
However if I change them I get message
set_property CONFIG.Load_Init_File true [get_bd_cells blk_mem_gen_1]
WARNING: [BD 41-721] Attempt to set value 'true' on disabled parameter 'Load_Init_File' of cell '/blk_mem_gen_1' is ignored
How can I load my memory?
11-17-2016 09:56 AM
11-17-2016 08:31 PM
When using IP integrator, the initialization in "BRAM Controller Mode" is done only through the MEM file. For more details, see Update MEM to Update Bit Files with MMI and ELF Data in Embedded Processor Hardware Design User Guide (UG898)
11-21-2016 02:28 AM
Hi I should add I am trying to do this so I load the Block Memory for Simulation - not for bitstream.
I believe that the way to do this is to edit the design in RTL Analysis tools not in IP Integrator which cannot do it.
I will report later on my experiments
11-27-2016 08:56 PM
I think it is not possible to initialize the memory in BRAM controller mode in simulation.
11-29-2016 04:05 AM
Not being able to load block memory for simulation is extremely troubling. Here is an example situation
If a design integrates a third party, or "own design" processor of some sort, it is extremely useful to be able to simulate the processor and a block RAM. For example if the processor does not boot, or behaves strangely.
Could you comment on the following workaround.....
......would it be possible to build a simulation including block memory and use a TCL script that acts at 0nS to read a file and force the memory array in the block memory to be initialised to the values in the file, line by line?