05-17-2017 07:47 AM
I was playing around with a simulation in Vivado 2017.1 and I arrived at this cryptic error:
ERROR: [VRFC 10-113] D:/Xilinx2017.1/Vivado/2017.1/data/xsim/ip/axi_bram_ctrl_v4_0_11/axi_bram_ctrl_v4_0_11.vdbl needs to be re-saved since blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6 changed
ERROR: [VRFC 10-147] axi_bram_ctrl_v4_0_11.axi_bram_ctrl failed to restore
For whatever reason, whatever I did modified the blk_mem_gen_v8_3_6 and fifo_generator_v13_1_4 simulation IP blocks:
Note the "Date Modified for the rest of the blocks -- I installed Vivado 2017.1 on 4/19/2017.
"You have to change ALL VHDL files in your design for "VHDL 2008" instead of "VHDL". Don't leave a single file as VHDL..."
But I do not know how to change all my VHDL files to use VHDL 2008 ...
05-17-2017 07:51 AM
I copied the blk_mem_gen_v8_3_6 and fifo_generator_v13_1_4 files from a co-workers Vivado 2017 install to D:\Xilinx2017.1\Vivado\2017.1\data\xsim\ip and this seemed to have fixed the issue.
I would still like an explanation of the root cause
05-17-2017 08:23 AM
You can use beyond compare to compare the working folder and not working one, and then you can have an idea on what are changed.
05-17-2017 09:05 AM
Looks like the problem has to do with how I am managing my IP. I was attempting to create a block called "SimDataFiller" in a configure/create IP project. In the same project, I created some simulation sources and a simulation-only board file (that has a block ram component in it). When I went to launch my simulation via the "launch_simulation" tcl command it would generate then call this script:
REM compile.bat @echo off set xv_path=D:\\Xilinx2017.1\\Vivado\\2017.1\\bin echo "xvlog -m64 --relax -prj sim_top_vlog.prj" call %xv_path%/xvlog -m64 --relax -prj sim_top_vlog.prj -log xvlog.log call type xvlog.log > compile.log echo "xvhdl -m64 --relax -prj sim_top_vhdl.prj" call %xv_path%/xvhdl -m64 --relax -prj sim_top_vhdl.prj -log xvhdl.log call type xvhdl.log >> compile.log if "%errorlevel%"=="1" goto END if "%errorlevel%"=="0" goto SUCCESS :END :SUCCESS
# compile vhdl design source files vhdl xil_defaultlib "../../../SimDataFiller_1.0/hdl/SimDataFiller_v1_0_M00_AXI.vhd" vhdl xil_defaultlib "../../../SimDataFiller_1.0/hdl/SimDataFiller_v1_0.vhd" vhdl textutil "../../../edit_SimDataFiller_v1_0.ip_user_files/bd/sim_block/ipshared/226b/example_designs/std_logic_textio.vhd" vhdl xil_defaultlib "../../../edit_SimDataFiller_v1_0.ip_user_files/bd/sim_block/ipshared/226b/hdl/SimDataFiller_v1_0_M00_AXI.vhd" vhdl xil_defaultlib "../../../edit_SimDataFiller_v1_0.ip_user_files/bd/sim_block/ipshared/226b/hdl/SimDataFiller_v1_0.vhd" vhdl xil_defaultlib "../../../edit_SimDataFiller_v1_0.ip_user_files/bd/sim_block/ip/sim_block_SimDataFiller_0_0/sim/sim_block_SimDataFiller_0_0.vhd" vhdl xil_defaultlib "../../../edit_SimDataFiller_v1_0.srcs/sim_1/bd/sim_block/ip/sim_block_SimDataFiller_0_0/synth/sim_block_SimDataFiller_0_0.vhd" vhdl blk_mem_gen_v8_3_6 "../../../edit_SimDataFiller_v1_0.srcs/sim_1/bd/sim_block/ipshared/4158/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd" vhdl xil_defaultlib "../../../edit_SimDataFiller_v1_0.srcs/sim_1/bd/sim_block/ip/sim_block_blk_mem_gen_0_1/synth/sim_block_blk_mem_gen_0_1.vhd" vhdl xil_defaultlib "../../../edit_SimDataFiller_v1_0.ip_user_files/bd/sim_block/ip/sim_block_axi_bram_ctrl_0_1/sim/sim_block_axi_bram_ctrl_0_1.vhd" vhdl xil_defaultlib "../../../edit_SimDataFiller_v1_0.srcs/sim_1/bd/sim_block/ip/sim_block_axi_bram_ctrl_0_1/synth/sim_block_axi_bram_ctrl_0_1.vhd" vhdl xil_defaultlib "../../../edit_SimDataFiller_v1_0.ip_user_files/bd/sim_block/hdl/sim_block.vhd" vhdl fifo_generator_v13_1_4 "../../../edit_SimDataFiller_v1_0.srcs/sim_1/bd/sim_block/ipshared/ebc2/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd" vhdl xil_defaultlib "../../../edit_SimDataFiller_v1_0.srcs/sim_1/bd/sim_block/hdl/sim_block_wrapper.vhd" vhdl xil_defaultlib "../../../SimDataFiller_1.0/example_designs/sim_top.vhd" # Do not sort compile order nosort
It looks like the "vhdl blk_mem_gen_v8_3_6 ...." and "vhdl fifo_generator_v13_1_4 ..." lines are the issue.
I can reproduce the issue with the minimal script:
%xv_path%/xvhdl -m64 --relax -prj blk_mem.prj -log xvhdl.log
where blk_mem.prj is
# compile vhdl design source files vhdl blk_mem_gen_v8_3_6 "../../../edit_SimDataFiller_v1_0.srcs/sim_1/bd/sim_block/ipshared/4158/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd" # Do not sort compile order nosort
So the question remains: why is it that, when running a simulation via the IP packager project, it over-writes the standard simulation IP files?
05-23-2017 08:48 PM
0.6 2017.1 Apr 14 2017 18:58:24 /wrk/2017.1/nightly/2017_04_14_1846317/packages/customer/vivado/data/ip/xilinx/blk_mem_gen_v8_3/simulation/blk_mem_gen_v8_3.v,1492224070,verilog,,,,STATE_LOGIC_v8_3;beh_vlog_ff_ce_clr_v8_3;beh_vlog_ff_clr_v8_3;beh_vlog_ff_pre_v8_3;beh_vlog_muxf7_v8_3;blk_mem_axi_read_wrapper_beh_v8_3;blk_mem_axi_regs_fwd_v8_3;blk_mem_axi_write_wrapper_beh_v8_3;blk_mem_gen_v8_3_6;blk_mem_gen_v8_3_6_mem_module;blk_mem_gen_v8_3_6_output_stage;blk_mem_gen_v8_3_6_softecc_output_reg_stage;read_netlist_v8_3;write_netlist_v8_3,,,/proj/xbuilds/2017.1_0415_1/infra/XSIM/lin/.cxl.ip/incl,,,,,
0.6 2017.1 Apr 14 2017 19:10:27 E:/Project_Files/rjmccabe/VivadoProjects/CHIL/sim_chil_dma_with_periph/sim_chil_dma_with_periph.srcs/sim_dma/bd/sim_block/ipshared/4158/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd,1495594898,vhdl2008,,,,bindec;blk_mem_axi_read_fsm;blk_mem_axi_read_wrapper;blk_mem_axi_regs_fwd;blk_mem_axi_write_fsm;blk_mem_axi_write_wrapper;blk_mem_gen_ecc_decoder;blk_mem_gen_ecc_encoder;blk_mem_gen_generic_cstr;blk_mem_gen_getinit_pkg;blk_mem_gen_mux;blk_mem_gen_pkg;blk_mem_gen_prim_width;blk_mem_gen_prim_wrapper;blk_mem_gen_prim_wrapper_init;blk_mem_gen_top;blk_mem_gen_v8_3_6;blk_mem_gen_v8_3_6_defaults;blk_mem_gen_v8_3_6_synth;blk_mem_gen_v8_3_6_synth_comp;blk_mem_input_block;blk_mem_min_area_pkg;blk_mem_output_block,,,,,,,,
As I explained in my earlier post, the core issue is Vivado's generation of the *_vhdl.prj file in the simulation directory --- I don't know much about the inner-workings of the simulation framework, but I see things break whenever i see things like:
vhdl2008 blk_mem_gen_v8_3_6 "../../../sim_chil_dma_with_periph.srcs/sim_dma/bd/sim_block/ipshared/4158/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd"
in that file.
05-24-2017 02:24 AM
Prj file list is generated based on simulation sources.
Can you check if you have added blk_mem_gen_v8_3_vhsyn_rfs.vhd manually to the project as VHDL 2008 type? If so, you can change it back to VHDL type.
12-11-2017 12:20 AM - edited 12-11-2017 12:28 AM
I'm getting this error in Vivado 2017.3. I am trying to simulate a block design with an AXI verification IP writing to a BRAM through an AXI BRAM controller. Without the BRAM controller the simulation works correctly, adding the BRAM controller breaks the sim and I get the error message.
I am not able to modify the properties of the blk_mem_gen_v8_3_vhsyn_rfs.vhd or axi_bram_ctrl_v4_0_rfs.vhd files since they are automatically managed by the block design. If I try adding the files manually and set them as VHDL 2008 the simulation get's stuck in the compile stage and never exits (left the process running for 3 hours). Normally the simulation takes 6 seconds to start without the BRAM controller. Is there a work around to get files in a block design compiled as VHDL 2008? The BRAM controller appears to be the only IP in the design that does not have verilog output files.
Any work around or information is welcome. Note: I did try copying over the files from a fresh 2017.3 install and that did not work for me.
07-20-2018 12:13 AM
I am also facing the same error in Vivado 2017.2. Is there any solution?