10-09-2019 07:17 AM
I have a vhdl delay_module which can be started from an superordinate module for initialization of an OLED display. The delay module should count microseconds, so there is a constant defined in vhdl code which setup the mathematical conversion from clockcycles to microseconds. For simluation issues I change the value of constant us_clk_cycles from 100 to 1. And then changing it back to 100 if I want to synthesize bitstream for hardware.
However I have now the problem that I set the value from 100 to 1 to do again simulation but the simulation does not recognize the change. I use Vivado 19.2. Even deleting the file and write it again doesn't help. I wonder what is the problem to read the correct value from it. When I look into the simulation and right click of the constant value and the "Go to Source" then editor will highlight the commented line "--constant us_clk_cycles : integer := 100; -- Hardware " which cannot be the true source because it is commented.
constant us_clk_cycles : integer := 1; -- Simulation
--constant us_clk_cycles : integer := 100; -- Hardware
Are there any knows issues regarding the reading in of constants in the simulation? I even have to worry that synthesises doesn't read the correct constant value because implementation failed (OLED display doesn't work anymore).
10-09-2019 07:30 AM
vivado is not perfect but is not that crappy. From my experience, sometimes some files get locked. try reset_project in the TCL console. Constants are just named literals. Try hardcoding it, it must work, otherwise nobody will use Vivado.
Another thing is if there are implementation errors, something is bad. Instead of saying "doesn't work anymore" tell us what the error is or what is doing differently from expected.
A delay module is probably a few HDL lines, so you might share it.
Last thing is that 'integers' are fine in simulation but for implementation is better to use std_logic_vector with the proper size to prevent things like a 32-bit counter for numbers from 0 to 100 (7 bit). Not only a waste of silicon, but it's also slower.
10-09-2019 07:38 AM - edited 10-09-2019 07:40 AM
Sorry, I had no bad intentions and I am still convinced of vivado. It just irritated me that the simulation doesn't take over the value of the constants in a reasonable way.
During the implementation I'm not yet sure where exactly the problem lies. I had first thought that the constant value might not be adopted correctly and that the initialization of the OLED display would fail because of that (the display worked before). For example, it is important for the display to wait 64 ms after configuring the Charge Pump, etc. Therefore the delay module was necessary.
Here is the code for the delay module:
---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity delay is Port ( clk : in STD_LOGIC; start_delay : in STD_LOGIC; delay_time_us : in STD_LOGIC_VECTOR(16 downto 0); delay_done : out STD_LOGIC); end delay; architecture Behavioral of delay is --constant us_clk_cycles : integer := 1; -- For Simulation constant us_clk_cycles : integer := 100; -- For Hardware type delay_states is (IDLE, PREP, COUNT, DONE); signal delay : delay_states := IDLE; signal delay_time_us_sig : STD_LOGIC_VECTOR(16 downto 0) := (others => '0'); signal clk_counter : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); signal us_counter : STD_LOGIC_VECTOR(16 downto 0) := (others => '0'); signal count_finish : STD_LOGIC := '0'; begin delay_process : process (clk) begin if (rising_edge(clk)) then case delay is when IDLE => delay_done <= '0'; if (start_delay = '1') then delay <= PREP; else delay <= IDLE; end if; when PREP => delay_time_us_sig <= delay_time_us; delay <= COUNT; when COUNT => if (count_finish = '1') then delay <= DONE; else delay <= COUNT; end if; when DONE => delay_done <= '1'; delay <= IDLE; when others => null; end case; end if; end process; counter_process : process(clk) begin if (rising_edge(clk)) then case delay is when COUNT => if (clk_counter = us_clk_cycles) then clk_counter <= (others => '0'); if (us_counter = delay_time_us_sig) then us_counter <= (others => '0'); count_finish <= '1'; else us_counter <= us_counter + '1'; end if; else clk_counter <= clk_counter + '1'; end if; when others => clk_counter <= (others => '0'); us_counter <= (others => '0'); count_finish <= '0'; end case; end if; end process; end Behavioral;
10-09-2019 08:14 AM
if (clk_counter = us_clk_cycles) then
clk_counter is STD_LOGIC_VECTOR(15 downto 0) but us_clk_cycles isn't.
Couldn't you define
constant us_clk_cycles : STD_LOGIC_VECTOR(15 downto 0) := d"100";
10-09-2019 10:19 AM