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Registered: ‎08-09-2018

Clock going unknown as it passes through higher levels of the design

I am trying to run a test level behavioral simulation which uses the test bench generated for a JESD204 RX core. I share the clocks for the JESD204 TX, RX, and PHY cores. 

The issue I am seeing is that the clock being generated looks fine inside the module that generates it. However, at the next higher level where it is used it goes unknown when it trys to go to the '1' state.

I suspect this may be due to the following statement I have in the next higher level of the design which sets the initial value of this signal at this level.

wire refclk = 1'b0; // DEBUG!!! Needs to be set to '0' for behavioral sim or
                             // Failure: ERROR:add_1 must be in range [-1,DEPTH-1]

However, if I do not have this statement in the code I get the error outlined in the above comment. Any suggestions?

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