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Registered: ‎04-26-2013

Clock modeling issue in 64-8bit serialiser (Input 64 bit data comes with clock_period of 6468 ps)

Hi,

 

I am writting a 64 bit to 8bit serialiser. The 64 bit data is coming with a clock of clock period (6468ps and I cant change it because its the data coming from Hardware module).

To sample the 64 bit data, I am sampling it 8 times before it changes to serialise it into separate 8-bit samples.

The problem arrise when I divide the clock period with 8 (which in my case becomes 808.5 ps).

Questasim takes this clock period as 809 ps and the clock wave which is generated is of 808 ps (As the rounding error also comes while generating the clock i.e (clock_period/2 = 0.404 ns instead of 0.40425 ns).

The current resolution of Questasim is in 'ns', I tried to change the resolution into 'fs' from its .ini file but it didnt affect the above pericision.

 

My clock_generator code is below where I have already added a delay of 4 ps at the end of each cycle to compensate the rounding error. Is there any better way to address this issue?

 

 

 

constant clk_period : time := 808.5 ps;      -- 6468/8 = 808.5

 

clk_process :process
    variable count : integer := 0;
   begin
        clk_int <= '0';
        count := count +1;
        if(count = 8) then
            wait for 0.004 ns;               --  [((8 x 0.808ns) + 0.004ns) = 6468 ps which is the required period]
            count := 0;
       end if;
        wait for clk_period/2;            -- This should be 0.40425 ns but Questasim makes it 0.404ns, hence creating a total period of
        clk_int <= '1';                        --  0.808 ns
        wait for clk_period/2;
   end process;

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