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Observer
Observer
1,270 Views
Registered: ‎12-31-2007

Clocking variable is read to -1 in submodule

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My environment:

Windows 10 64-bit build 16299.248

Vivado 2017.4

 

When I run the behavioral simulation with the following code with Vivado Simulator 2017.4. I find the clocking variable cb.t is read to -1 sometimes. However, the signal t is unsigned.

`timescale 1 ns / 1 ps

module C(input t, input clk);

    default clocking cb @(posedge clk);
        input t;
    endclocking

    initial begin
        #0;
        forever begin
            @(posedge clk);
            $display("cb.t == %d", cb.t);
            if(cb.t == -1)
                $fatal(1, "Error!");
        end
    end
endmodule

module Tb;
    // Clock period.
    parameter real clk_p = 10;
    // Clock half period
    parameter real clk_hp = (clk_p)/2;
    // Delay for Xilinx FPGA GSR.
    parameter xilinx_gsr = 100;

    logic nreset;
    logic clk;
    logic t;

    initial begin
        nreset = 0;
        #xilinx_gsr;

        #(clk_p);
        nreset = 1;

        #300;
        $finish;
    end

    initial begin
        t = 0;
        #100;
        t = 1;
        #100;
    end

    initial begin
        clk = 0;
        #xilinx_gsr;
        @(posedge nreset);
        #8;
        forever #clk_hp clk = ~clk;
    end

    C c0(.*);
endmodule

The Tcl Console will show:

 

cb.t ==  x
cb.t == -1
Fatal: Error!

 

However, Synopsys VCS 2017.12 seems to correctly simulate the code and print these:

cb.t == 0
cb.t == 1
cb.t == 1
...

Is this a Vivado bug? If it is, please Xilinx fix it. Thanks.

 

 

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Xilinx Employee
Xilinx Employee
1,737 Views
Registered: ‎08-10-2015

hi @zxvc,

 

This seems to be the bug in Vivado simulator. Issue reported to the factory.

 

 

Thanks,

Sunilkumar

View solution in original post

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4 Replies
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Xilinx Employee
Xilinx Employee
1,738 Views
Registered: ‎08-10-2015

hi @zxvc,

 

This seems to be the bug in Vivado simulator. Issue reported to the factory.

 

 

Thanks,

Sunilkumar

View solution in original post

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Observer
Observer
1,250 Views
Registered: ‎12-31-2007
Thank you.
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Xilinx Employee
Xilinx Employee
1,238 Views
Registered: ‎08-10-2015

Hi @zxvc,

 

As a work around, please update the module ports with datatypes mentioned below

module C(input logic t, input logic clk);

 

Design working as expected  with the above change.

 

 

Thanks,

Sunilkumar

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Observer
Observer
1,231 Views
Registered: ‎12-31-2007
Thanks. The workaround works.
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