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dmitry1417
Explorer
Explorer
8,451 Views
Registered: ‎02-24-2016

Code Coverage -> how to?

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Hi All,

 

How can I generate a Code Coverage report for Vivado simulations?

 

Where can I see some examples? .

 

Thank you!

 

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vijayak
Xilinx Employee
Xilinx Employee
14,786 Views
Registered: ‎10-24-2013

Hi @dmitry1417

Code coverage is not yet supported by Vivado simulator and is in roadmap.

Thanks,Vijay
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vijayak
Xilinx Employee
Xilinx Employee
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Registered: ‎10-24-2013

Hi @dmitry1417

Code coverage is not yet supported by Vivado simulator and is in roadmap.

Thanks,Vijay
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austin
Scholar
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8,445 Views
Registered: ‎02-27-2008

d,

 

There is documentation for code coverage of your sources for c/c++ using HLS (ug998).  Is that what your are looking for?  or is the coverage fort you verilog or VHDL (quite a different task)?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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dmitry1417
Explorer
Explorer
8,396 Views
Registered: ‎02-24-2016

Actually I need some indication how much my TestBench cover the RTL functionality.

 

The RTL is written in Verilog, TestBenches are also.

 

I'm using Vivado v2015.4 for my simulations. 

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nagabhar
Xilinx Employee
Xilinx Employee
8,385 Views
Registered: ‎05-07-2015

hi @dmitry1417

 

As mentioned before by Vijay, this is not yet supported in Vivado.
You will have go  for a  third party simulator like Questa sim which has the code coverage analysis feature.

Thanks
Bharath
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vijayak
Xilinx Employee
Xilinx Employee
8,359 Views
Registered: ‎10-24-2013

Hi @dmitry1417

 

Hope that answers your query. Please close the thread by marking the solution in the interest of other users.

Thanks,Vijay
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sanjivgarg
Adventurer
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Registered: ‎12-10-2014

Has code coverage for Vivado simulator been added yet?

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