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Observer
Observer
9,584 Views
Registered: ‎03-17-2014

ComMsgMgrException: type error near %s

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I am using the block memory genrator to instiate a block ram in my design and when i attempt to simulate the design i get the following error:

 

ComMsgMgrException: type error near %s ; expected type %s: Invalid c_string in format.

ERROR: [VRFC 10-1472] type error near %s ; expected type %s

 

This error mentions nothing about the block ram generator or my code, but I know it is related to the block ram generator because when i remove the block ram from my code this error goes away. 

 

I am not realy sure how to get around this. I have tried regenerating the output product for this block ram and even removed it from the project and put it back agian. I cannot find anything on the internet with this same error message.... 

 

Anyone else seen this?

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Xilinx Employee
Xilinx Employee
15,921 Views
Registered: ‎09-20-2012
Hi,

Follow the steps below.

1. Set the "target language" to VHDL in project settings.
2. Right click on the IP and do "reset output products" followed by "generate output products". This will generate the template in vhdl language.

Thanks,
Deepika.
Thanks,
Deepika.
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Teacher
Teacher
9,572 Views
Registered: ‎03-31-2012
which simulator are you using? Also how are you instantiating the generated block ram? Did you use the instantiation template generated exactly?
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Observer
Observer
9,550 Views
Registered: ‎03-17-2014

Thanks for the reply

 

I am using ISIM or the default vivado simulator... not sure if that is called ISIM anymore.

 

My instantiation is shown below:

 

blk_mem_gen_0_inst : ENTITY work.blk_mem_gen_0
PORT map(
--
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,

--
clkb => clka,
enb => 1,
web => 0,
addrb => Data_I,
dinb => dummy,
doutb => data_out_sig
);

 

 

I didn't get this instantiation from a template rather created it myself base on the toplevel "blk_mem_gen_0.vhd" in vivado.

 

In ISE there was feature that would create a instaition template for you but it seems this is missing in vivado... If there is a way to autogenerate and instatiion template in vivado i would like to know about it.

 

Thanks 

 

 

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Teacher
Teacher
9,545 Views
Registered: ‎03-31-2012
coregen gives you a instantiation template when you create the ip. It usually has an extension .veo. Checkout the directory where you put the IP.
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Moderator
Moderator
9,536 Views
Registered: ‎07-21-2014

Hi,

 

You can find generated "Instantiation Template" under IP Source. Refer below snapshot:

 

Capture.PNG

 

Thanks,
Anusheel
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Observer
Observer
9,518 Views
Registered: ‎03-17-2014

ahh.

 

that is good to know but the instaition template is in verilog and i am using vhdl. I tried punching around to find out how to change the instiation template to vhdl, but cant seem to find that...?

 

My project is set to use VHDL, but it still is instiationing the template in verilog?

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Xilinx Employee
Xilinx Employee
15,922 Views
Registered: ‎09-20-2012
Hi,

Follow the steps below.

1. Set the "target language" to VHDL in project settings.
2. Right click on the IP and do "reset output products" followed by "generate output products". This will generate the template in vhdl language.

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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Observer
Observer
9,493 Views
Registered: ‎03-17-2014

Thanks

 

This seemed to solve the problem once i used this instation template.

 

Thanks All!

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