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Visitor orohev
Visitor
1,906 Views
Registered: ‎06-15-2017

Comparing simulation results to known values

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Hi all,

 

I would like to validate my design by comparing the results of the simulation (behavioral and post-implementation) with the expected values.

 

I'm implementing a Verilog code to program Artix-7 FPGA (Arty board).

 

My questions are the following:

1. I would like to avoid changes in the Verilog code. Is there a way to export the data into .CSV or .TXT formats (or any other readable format)? I only found a way to export the ILA results (and not into .CSV format).

2. in the absence of suitable solution, will system functions work on post-implementation simulation (such as $display, $fopen, $fwrite)?

 

Thanks in advance!

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Scholar dgisselq
Scholar
3,249 Views
Registered: ‎05-21-2015

Re: Comparing simulation results to known values

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Have you considered using Verilator at all?  There's a pretty complete simulation of an OpenArty project using Verilator on github.  As for the resulting format, results from the simulation are stored in the VCD format.  You can find a tutorial here describing how to create (and to some extent how to decode) the format.  In many ways the VCD format is much better than any CSV format, since only variables that change need to be placed within VCD.  (A recent CSV file I had was reformatted into CSV, going from GB of data down to a couple hundred KB).  VCD files are text files, too, so you can open them up in your editor--even if they aren't in English.

Dan

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Scholar dgisselq
Scholar
3,250 Views
Registered: ‎05-21-2015

Re: Comparing simulation results to known values

Jump to solution

Have you considered using Verilator at all?  There's a pretty complete simulation of an OpenArty project using Verilator on github.  As for the resulting format, results from the simulation are stored in the VCD format.  You can find a tutorial here describing how to create (and to some extent how to decode) the format.  In many ways the VCD format is much better than any CSV format, since only variables that change need to be placed within VCD.  (A recent CSV file I had was reformatted into CSV, going from GB of data down to a couple hundred KB).  VCD files are text files, too, so you can open them up in your editor--even if they aren't in English.

Dan

Visitor orohev
Visitor
1,776 Views
Registered: ‎06-15-2017

Re: Comparing simulation results to known values

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Thanks for the reply!

 

I've found another possible solution thanks to your idea:

1. Save the waveform database into a VCD format

2. Open the VCD file in a different simulator.

3. Export the waveform data into a .CSV file

 

This is done easily by opening a new simulation in Vivado, configure all the needed forces and then by typing the commands:

1. open_vcd

2. log_vcd

3. run 2s

4. close_vcd (this is crucial as the file saves only after this command).

The file will be available in the folder ...Project_Name\Project_Name.sim\sim_1\impl\func under the name dump.vcd

 

I know VCD is a text file but the file was unreadable in notepad++.

The VCD output file of a 2s simulation was ~8GB but the CSV file was only 11MB (as only small portion of the signals were needed)

 

I took the idea from here and from your idea to store the results in VCD format.

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