UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor larrypap
Visitor
3,021 Views
Registered: ‎04-14-2012

Compilation error in CAM memory cam_v5_1 and cam_v6_1

I use CAM memory cam_v5_1 from LogiCore (in ISE v10.1 SP3) and I have compilation error (in ISim).

 

ERROR:HDLCompiler:410 - "K:/IP3_K.12/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/cam_v5_1.vhd" Line 834. Expression has 16 elements ; expected 4

ERROR:Simulator:777 - Static elaboration of top level VHDL design unit tb_file_read in library work failed

 

When remove the CAM statement (my_CAM), works properly. When I put it, I have errors ….. any idea?

 

In .coe file I have the correct data

 

MEMORY_INITIALIZATION_RADIX=2;

MEMORY_INITIALIZATION_VECTOR=

00000000000000000000000000000000,

01000010000000000000000000000001,

00000000000000000000000000000000,

00000000000000000000000000000000,

00000000000000000000000000000000,

00000000000000000000000000000000,

00000000000000000000000000000000,

00000000000000000000000000000000,

00000000000000000000000000000000,

00000000000000000000000000000000,

00000000000000000000000000000000,

00000000000000000000000000000000,

00000000000000000000000000000000,

00000000000000000000000000000000,

00000000000000000000000000000000,

00000000000000000000000000000000;

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity TB_FILE_READ is

end TB_FILE_READ;

.

.

component cam2e

            port (

                                    clk: IN std_logic;

                                    din: IN STD_LOGIC_VECTOR(31 downto 0);

                                    busy: OUT std_logic;

                                    match: OUT std_logic;

                                    match_addr: OUT STD_LOGIC_VECTOR(3 downto 0));

end component;.

.

.

signal data_out_A:      std_logic_vector(31 downto 0) := (others => '0');

.

.

-- cam signals

signal s_asxeto: std_logic :='0';

signal s_nai_yparxei: std_logic :='0';

signal s_i_dieythinsi: std_logic_vector(3 downto 0);

.

.

 

my_CAM : cam2e

port map(

                                                clk                               => clk,

                                                din                               => data_out_A,

                                                busy                             => s_asxeto,

                                                match                          => s_nai_yparxei,

                                                match_addr                => s_i_dieythinsi

                                    );

.

.

 

 

I have the same errors when use the cam_v6_1

 

ERROR:HDLCompiler:410 - "K:/IP3_K.12/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/cam_v6_1.vhd" Line 1241. Expression has 16 elements ; expected 4

ERROR:Simulator:777 - Static elaboration of top level VHDL design unit tb_file_read in library work failed

0 Kudos
1 Reply
Visitor larrypap
Visitor
2,999 Views
Registered: ‎04-14-2012

Re: Compilation error in CAM memory cam_v5_1 and cam_v6_1

Hi!

 

I found the problem!

 

In the beginning in my project I used the first  “Binary Encoded” in my_CAM (cam2e), the compile was successful!

When I use “Single Much Unencoded” and “Multi Much Unencode” (because I want to see results) the compile was again successful!

When I restored setting in “Binary Encoded” then the problem and the messages occurred

 

ERROR:HDLCompiler:410 - "K:/IP3_K.12/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/cam_v6_1.vhd" Line 1241. Expression has 16 elements ; expected 4

ERROR:Simulator:777 - Static elaboration of top level VHDL design unit tb_file_read in library work failed

 

And remain there ………..  :/

 

Yes I know I can use encoder to find the address, but I prefer the first option “Binary Encoded”.

 

Thanks!!

0 Kudos