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Visitor
Visitor
7,117 Views
Registered: ‎05-22-2012

Core Generator FIFO simulation.

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Dear all.

 

I would like to ask for your help.

I am using ISE webpack and I am having some problems. I have used core generator in order to implement a sunchronous FIFO for my project and I am trying to test bench it!I ve written a very simple test bench in order to see how ti works.

 

To begin when tried to build a 8.5 fifo on my laptop when it came into simulate the test bench of the project I would get an error saying that the behavioral simulation is not supported by Virtex 5 etc and that I should use structural simulation and that I can do this by going to the core manager and changing the settings.

 

At my university's ISE ( I think that they dont have a licence as well or something) I was in the beginning having the same message but after teasing with the settings I finally made it work with out having the error above.

 

When I tried to do the same thing on my laptop and by doing the same steps as I did in the uni's pc I would always have the same message.

 

Either way the 8.3 FIFO generated at my Uni's pc works ok on my laptop so for now I am using this for test benching.

 

Now to the second problem. In my test bench I am trying to make things work to see the FIFO in action.

 

My stimulus process is something as simple as this :  

din<="01010100";
    wr_en<='1';
    empty<='0';
    rd_en<='1';
    rst<='1';

 

I mean just to see it working to begin with.

And I am getting this:

[URL=http://imageshack.us/photo/my-images/98/fifosim.jpg/][IMG]http://img98.imageshack.us/img98/4697/fifosim.jpg[/IMG][/URL]

Uploaded with [URL=http://imageshack.us]ImageShack.us[/URL]

 

Any thoughts on how to get it to have a valid empty signal and see the input data read out?

 

With regards.

 

nick

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Highlighted
Professor
Professor
8,985 Views
Registered: ‎08-14-2007

Re: Core Generator FIFO simulation.

Jump to solution

Your stimulus process sets the rst signal to 1 and leaves it there.  rst is active high,

and while active the FIFO will stay reset.  You need to release reset after some time like:

 

stim_proc: process
   begin        
   din<="00001111";
    wr_en<='1';
    rst<='1';
    rd_en<='1';
    wait for clk_period * 10;

    rst <='0';
    wait;
end process;

 

-- Gabor

-- Gabor

View solution in original post

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Visitor
Visitor
7,109 Views
Registered: ‎05-22-2012

Re: Core Generator FIFO simulation.

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I ve managed to solve the first problem but I cannot test bench the FIFO correctly.

 

Any sugestions please fire away!

 

http://imageshack.us/photo/my-images/98/fifosim.jpg/

 

This is what I get.

 

cheers

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Highlighted
Professor
Professor
7,101 Views
Registered: ‎08-14-2007

Re: Core Generator FIFO simulation.

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If you need help on the test bench I would suggest posting your code.  If you are really doing what

you showed in the first post, then I would suggest getting rid of any lines in the test bench that

make an assignment to 'empty' like:

 

empty <= '0';

 

If both the test bench and the unit under test are driving the signal, you'll see an 'X' in simulation.

 

-- Gabor

-- Gabor
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Highlighted
Visitor
Visitor
7,094 Views
Registered: ‎05-22-2012

Re: Core Generator FIFO simulation.

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Hello there and thnx alot for your answer!!

I havent written the test bench code my self!

I have just used the VHDL Test bench ISE provides. I ve added a source to the fifo created by the core generator and basically I have the test bench ready and by editing the stimulus proccess in order to see how it works. So I must trigger some signals in order to see it working! The problem is that even if I just put some data in and run the structural simulation nothing happens to the other signals!


The code of the test bench is the following (created by ISE) :

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY fifo_tb IS
END fifo_tb;
 
ARCHITECTURE behavior OF fifo_tb IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT fifo
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         din : IN  std_logic_vector(7 downto 0);
         wr_en : IN  std_logic;
         rd_en : IN  std_logic;
         dout : OUT  std_logic_vector(7 downto 0);
         full : OUT  std_logic;
         empty : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal din : std_logic_vector(7 downto 0) := (others => '0');
   signal wr_en : std_logic := '0';
   signal rd_en : std_logic := '0';

     --Outputs
   signal dout : std_logic_vector(7 downto 0);
   signal full : std_logic;
   signal empty : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: fifo PORT MAP (
          clk => clk,
          rst => rst,
          din => din,
          wr_en => wr_en,
          rd_en => rd_en,
          dout => dout,
          full => full,
          empty => empty
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;
 

   -- Stimulus process


   stim_proc: process
   begin        
   din<="00001111";
    wr_en<='1';
    rst<='1';
    rd_en<='1';
    

      wait;
   end process;


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Highlighted
Professor
Professor
8,986 Views
Registered: ‎08-14-2007

Re: Core Generator FIFO simulation.

Jump to solution

Your stimulus process sets the rst signal to 1 and leaves it there.  rst is active high,

and while active the FIFO will stay reset.  You need to release reset after some time like:

 

stim_proc: process
   begin        
   din<="00001111";
    wr_en<='1';
    rst<='1';
    rd_en<='1';
    wait for clk_period * 10;

    rst <='0';
    wait;
end process;

 

-- Gabor

-- Gabor

View solution in original post

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Highlighted
Visitor
Visitor
7,077 Views
Registered: ‎05-22-2012

Re: Core Generator FIFO simulation.

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Thnx mate I got it to work!

 

With a bit of twicking here and there I can see the FIFO working as it should!

 

cheers: )

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