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Creating a test bench with Two FPGA

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Adventurer
Posts: 77
Registered: ‎07-20-2009
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Creating a test bench with Two FPGA

Hello,

This might be a basic question. But please help.

I have two FPGA designs(actually two boards). One with Kintex 7 and other with UltraScale. There are data transfer between two FPGA boards .

I have separate projects for implementation.

I want to create a simulation environment containing two FPGA's and MIMIC the data transfer in simulation.

Can I do that? How I can do it in Vivado?

 

Regards

Anoop


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Teacher
Posts: 5,122
Registered: ‎03-31-2012

Re: Creating a test bench with Two FPGA

@anoopjoseph this maybe a case where you do a non-project based simulation setup and precompile libraries for both parts. Xilinx is usually quite careful about renaming cells which have different behaviors in different parts so there should be minimum (if any) amount of name collision. If you use manual  project generation, you can use add_files, add_ip etc commands to add files from both projects including the wrappers.

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Teacher
Posts: 5,122
Registered: ‎03-31-2012

Re: Creating a test bench with Two FPGA

[ Edited ]

@anoopjoseph that should be quite doable especially If your current simulation setup starts at chip level for both projects, all you need is to instantiate both chips in a new testbench (or copy one testbench and add the other chip to it). Maybe you are asking a different question than I'm thinking ...

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Adventurer
Posts: 77
Registered: ‎07-20-2009

Re: Creating a test bench with Two FPGA

Thanks muzaffer for the reply.

 

I do not have a simulation environment now. I am doing data transfer between FPGA on board(hardware).I want to create a fresh simulation environment containing to FPGA part numbers.

I want to do simulation in Vivado with ISIM. How can we create a project in VIVADO with two FPGA part number?

Please 

 

Regards

Anoop

Teacher
Posts: 5,122
Registered: ‎03-31-2012

Re: Creating a test bench with Two FPGA

@anoopjoseph Vivado doesn't have ISIM, I am not sure if there is a name for the simulator in Vivado but I think it's called xsim.

In any case, you should create a testbench and instantiate both chips in it. I am not sure if you can use the GUI to do this but a text editor beats any GUI any day of the week and twice on sunday. If your current projects are in Vivado, you should be able to use the wrapper created by Vivado as the top level of the chip(s)

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Adventurer
Posts: 77
Registered: ‎07-20-2009

Re: Creating a test bench with Two FPGA

Thanks for the input. I will try.

But I am not sure in my case, it will work. Because my both projects are Block Design based and have HDL Wrapper as TOP module.Even if I instantiate both wrapper in a text file, I need to open VIvado and add both wrapper and associated files in project. Since both wrapper contains block design for different part numbers, I do not know how the tool interpret it.

 

Highlighted
Teacher
Posts: 5,122
Registered: ‎03-31-2012

Re: Creating a test bench with Two FPGA

@anoopjoseph this maybe a case where you do a non-project based simulation setup and precompile libraries for both parts. Xilinx is usually quite careful about renaming cells which have different behaviors in different parts so there should be minimum (if any) amount of name collision. If you use manual  project generation, you can use add_files, add_ip etc commands to add files from both projects including the wrappers.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
Adventurer
Posts: 77
Registered: ‎07-20-2009

Re: Creating a test bench with Two FPGA

Thank you muzaffer for your advise.

I created two simple projects with different FPGA families and  could able to simulate in non project mode with xsim.

I shall try this method to my original projects.

 

Regards

Anoop