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739 Views
Registered: ‎10-06-2018

D Flip Flop

Hi!

   I have designed D flipflop, but its simulation results are not as per expected, there is no delay. can anybody tell reason what could be the problem.

  Verilog code and simulation results are attached,  give feed back on it.

// flip flop

module cic(D,clk,sync_reset,Q);
input [3:0] D; // Data input
input clk; // clock input
input sync_reset; // synchronous reset
output reg [3:0] Q; // output Q
always @(posedge clk)
begin
if(sync_reset==1'b1)
Q <= 4'b0;
else
Q <= D;
end
endmodule

 

// testbeanch

module tb();
reg [3:0] D; // Data input
reg clk; // clock input
reg sync_reset; // synchronous reset
wire [3:0] Q; // output Q

cic c(.D(D), .clk(clk), .sync_reset(sync_reset), .Q(Q));

always #5 clk=~clk;

initial begin clk=0; sync_reset=0;
#15 D=5;
#10 D=2;
#20 D=7;
#10 D=14;
#20 D=15;
#10 D=12;
end
endmodule

ff.JPG
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16 Replies
Scholar richardhead
Scholar
724 Views
Registered: ‎08-01-2012

Re: D Flip Flop

This is because the input stimulus is not synchronised to the clock. Your D input changes 1 delta before the clock edge, making it look like there is no delay.

Change the input stimulus to wait for the clock edge rather than abosule time:

initial begin clk=0; sync_reset=0;
@(posedge clk);
D=5;
@(posedge clk);
D=2;
@(posedge clk);
D=7;
@(posedge clk);
D=14;
@(posedge clk);
D=15;
@(posedge clk);
D=12;
end
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715 Views
Registered: ‎10-06-2018

Re: D Flip Flop

hi richardhead!

Thank you for your reply sir,

    what ever you have told, i did those changes in code, but still i am unable to see any changes in result. 

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Moderator
Moderator
678 Views
Registered: ‎11-09-2015

Re: D Flip Flop

HI narendrandesainath@gmail.com 

Can you share your new waveform?

This is probably due to the delta of the simuation (refer to UG900 p228).What I would do is to change the value in your test bench during negative edges:

initial begin clk=0; sync_reset=0;
@(negedge clk);
D=5;
@(negedge clk);
D=2;

Or you can also add a small delay after the clock edge to simulate the propagation delay you would have in HW:

initial begin clk=0; sync_reset=0;
@(posedge clk);
#10ps
D=5;
@(negedge clk);
#10ps
D=2;

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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651 Views
Registered: ‎10-06-2018

Re: D Flip Flop

Hi Sir! 

  The data change at negative clock i have simulated, and there will be a only half cycle delay ( first figure). and aslo simulated 2nd one ( i.e giving delay values), in this i did not fine any changes.I have attached result, please find.

This delay problem i am facing only in simulation, in implementation its working as per expected

negativeedge.JPG
posedge.JPG
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Moderator
Moderator
614 Views
Registered: ‎11-09-2015

Re: D Flip Flop

Hi narendrandesainath@gmail.com 

The result with negative edges is expected. The data out is outputed on a rising edge.

And it is expected that in HW the results are different because there is a propagation delay. If you add few ps delay as I mentioned in my second suggestion, you should see what you are looking for.

This is only the way you vizualize things.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
596 Views
Registered: ‎04-01-2008

Re: D Flip Flop

I am going to high-jack this thread, because I see something very similar in a simulation I am doing.  See my snippet of code below.  In this code, I am attempting to register the reset signal, and then latch an address on a rising edge of a signal. 

Code:

image.png

 

 

 

 

 

 

 

 

 

 

The problem is, in the simulation, the signal "cpu_burst_reset_reg" is not a delayed version of "cpu_burst_reset".. 

 

image.png

 

 

 

This behavior is not normal for a simulation.  You should see the registered version toggle on the next clock after the initial signal. 

Can someone try to explain what is going on here?

Thanks.

Jesse C.

 

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Xilinx Employee
Xilinx Employee
569 Views
Registered: ‎07-16-2008

Re: D Flip Flop


@jechambe-koe  已写:

I am going to high-jack this thread, because I see something very similar in a simulation I am doing.  See my snippet of code below.  In this code, I am attempting to register the reset signal, and then latch an address on a rising edge of a signal. 

Code:

image.png

 

 

 

 

 

 

 

 

 

 

The problem is, in the simulation, the signal "cpu_burst_reset_reg" is not a delayed version of "cpu_burst_reset".. 

 

image.png

 

 

 

This behavior is not normal for a simulation.  You should see the registered version toggle on the next clock after the initial signal. 

Can someone try to explain what is going on here?

Thanks.

Jesse C.

 


As correctly indicated by others, this is caused by delta delay and race condition in event based simulator.

In the above example, how is cpu_burst_reset driven? If it's not synchronized to the same clock but whereas changed at the same time as rising clock edge, you'll possibly see what you get.

 

-------------------------------------------------------------------------
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Adventurer
Adventurer
546 Views
Registered: ‎04-01-2008

Re: D Flip Flop

In this example, the main input signal, "cpu_burst_reset" is driven by the CPU_CLOCK signal, but just in another component.

When doing a behavioral simulation, which this is, there shouldn't be any delta delays.  This should be a pure logic simulation with ideal conditions.  This is how it has typically worked in the past with Vivado, Modelsim, etc. correct?

Thanks.

Jesse

 

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Scholar richardhead
Scholar
538 Views
Registered: ‎08-01-2012

Re: D Flip Flop

@jechambe-koe 

Without the testbench code and module code, we will not know what the problem is.

It looks like a delta race to me.

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532 Views
Registered: ‎10-06-2018

Re: D Flip Flop

While posting quire I have included both module and test bench, I suggest to look back. 

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Scholar drjohnsmith
Scholar
527 Views
Registered: ‎07-09-2009

Re: D Flip Flop

What do yo uknwo abotu simulators / the tools and delta delays ?

Delta delay is how the simulator works.

 

this  guy , with a great mug shot on the fornt page, has a nice blog on it..

https://vhdlwhiz.com/delta-cycles-explained/

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar drjohnsmith
Scholar
522 Views
Registered: ‎07-09-2009

Re: D Flip Flop

I shoudl just add, ALL HDL simulators are the same with this delta idea.

be that Verilog, SystemVerilog,   VHDL  

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Adventurer
Adventurer
476 Views
Registered: ‎04-01-2008

Re: D Flip Flop

I learn something new every day!  

This Delta cycle in the simulation was my issue. 

I appreciate that link about the Delta cycles, specifically about the assigning of a clock signal to another another signal.  This is exactly what I did in the other component which had the clock, I did a CPU_CLK_OUT <= CPU_CLK.  Then the reset signal that was being generated in that component, did NOT have a signal assignment. 

I added a signal assignment to the RESET signal, so that it matches the CLK signal assignment, and now it works as I would expect. 

I appreicate the help with this. 

Jesse C.

Scholar drjohnsmith
Scholar
460 Views
Registered: ‎07-09-2009

Re: D Flip Flop

kudos to you for getting back
this HDL is an interesting world,
I've been in it for 40 plus years, and I still keep finding new bits...
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Historian
Historian
442 Views
Registered: ‎01-23-2009

Re: D Flip Flop

I shoudl just add, ALL HDL simulators are the same with this delta idea.

be that Verilog, SystemVerilog, VHDL

While the net result is more or less the same, Verilog/SystemVerilog do not have the concept "delta cycle". The event queue system in Verilog/SystemVerilog is defined by the language reference manual (LRM), and isn't based around the "delta cycle" concept. It does, however, have the concept of "non-determinacy of concurrent events" - basically, two events of the same "type" that are schedule for the same simulated time will be processed in a "non-deterministic" order - A may be processed before B or B may be processed before A - both are legal implementations of simulators. Of course, the event management is pretty complex, and there are lots of other factors regarding how (and when) events A and B get into the event queue...

Some simulators that are running Verlog/SystemVerilog may report "delta cycles", but these are really "iterations of the promotion of events to the active queue". Contrast this with VHDL, where the LRM describes the concept of delta cycles and how simulators must work regarding delta cycles.

But, in the end, you can end up with the same problem in Verilog/SystemVerlog - you can get a race condition of equivalent events in the same "modelled" time cycle, and hence the simulation may not perform as you expect....

Avrum

Scholar watari
Scholar
424 Views
Registered: ‎06-16-2013

Re: D Flip Flop

Hi @jechambe-koe 

 

Nice work !

 

Here are TIPS about delta delay for you, somebody might already mention.

 

- "Delta delay" is simulator job.

- (However) it depends on description of RTL.

- Perhaps, it might occur mixed simulation with RTL and netlist design.

 

So, I suggest you to take care of them and image a behaviour of your description.

 

Best regards,

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