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Voyager
Voyager
4,877 Views
Registered: ‎05-09-2008

DCM phase shift problem ...

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Hi,

 

I use ISE 10.1 with SP3. I have a little problem with DCM Phse Shift simulation (ISIM). I have made simple project with only one DCM with clock input of 64MHz. DCM make 64 MHz plus 64 MHz 90°. At all this clock i want apply a Phase Shift of "1nS", for this clock value is "17".

 

When I make the simulation clock has no phase shift, why ?

 

DCM Phase Shift

 

secureasm

 

 

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Xilinx Employee
Xilinx Employee
6,060 Views
Registered: ‎08-02-2007

Re: DCM phase shift problem ...

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from the screenshot I  can see that the clock input is not 64mhz

Please make sure you have made CLOCK input correct and it should be the same as what you set in the DCM

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Xilinx Employee
Xilinx Employee
6,061 Views
Registered: ‎08-02-2007

Re: DCM phase shift problem ...

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from the screenshot I  can see that the clock input is not 64mhz

Please make sure you have made CLOCK input correct and it should be the same as what you set in the DCM

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Voyager
Voyager
4,845 Views
Registered: ‎05-09-2008

Re: DCM phase shift problem ...

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Hi yangliiris,

 

thanks for your replay.

 

What you say is true  :smileysad: I just realized I had not seeing the fault clock drive.

 

I hope does not happen again.

 

Thanks.

 

secureasm

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Visitor tiaoz
Visitor
4,092 Views
Registered: ‎05-28-2012

Re: DCM phase shift problem ...

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I have some problems about the phase shift. The detailed questions are listed below.

 

I use Xilinx ISE 13.1 integrated Modelsim 6.6F to do simulation. I set a fixed phase shift 1.211ns for the input clock and the CLKFX (one of the DCM's output).  In the behaviroal simulation, the phase gap between them in the waveform is right. But

in the p&r simulation, the phase gap become 4.887ns and there is phase gap between clk and regaclk. It seems that the p&R simulation is wrong. I donnot know why there is an error in it. (The figures are in the attached file)

Thank you for your help.

 

Mao  

 

 

source code:

module testdcm( regaclk, shadowregaclk, clk, clk2x, lockedout, RST_IN, CLK90_OUT );

output regaclk,        shadowregaclk, lockedout;

 input  clk, RST_IN; output clk2x, CLK90_OUT;

wire inver_RST_IN;

assign inver_RST_IN = ~RST_IN;

dcm1 dcm1a (     .CLKIN_IN(clk),  

 .RST_IN(inver_RST_IN),  

   .CLKFX_OUT(shadowregaclk),

    .CLKIN_IBUFG_OUT(regaclk),    

 .CLK0_OUT(clk0out),  //not have clk0out before

    .CLK2X_OUT(clk2x),  

 .CLK90_OUT(CLK90_OUT),    

 .LOCKED_OUT(lockedout)   

  );

   endmodule

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