DDR memory access from PL simulation

[antonio.cerruto@astrel-instruments.com]

Hello,

I'd like to see in simulation some activity on DDR port (from ZYNQ PS) when writing data generated by PXL_TO_AXI_0 (RTL block).

I see on simulation proper AXI cycles up to the PS S_AXI_HP0 .

I see on simulation proper data ready for transfer toward DDR pins inside the DDRC of the PS.

But DDR lines are always "Z"

What's wrong? Is it possible to perform this kind of RTL simulation without any code running on the PS processor?

Thanks to all

Antonio

[antonio.cerruto@astrel-instruments.com · Accepted solution]

It seems that to check DDR interface we can simply use VIP:

so I wrote on the test bench the following VIP commands:

MPF_01_TB.MPF_01_BD_inst.MPF_01_BD_i.processing_system7_0.inst.read_mem(32'h2000_0000, 4, ddr_read_data);
$display ("%t, data read from DDR = h%x",$time, ddr_read_data); MPF_01_TB.MPF_01_BD_inst.MPF_01_BD_i.processing_system7_0.inst.read_mem(32'h2000_0004, 4, ddr_read_data);
$display ("%t, data read from DDR = h%x",$time, ddr_read_data); MPF_01_TB.MPF_01_BD_inst.MPF_01_BD_i.processing_system7_0.inst.read_mem(32'h2000_0008, 4, ddr_read_data);
$display ("%t, data read from DDR = h%x",$time, ddr_read_data); 

...

and can check on the TCL Console

[4500] : *ZYNQ_VIP_INFO : Starting Address(0x20000000) -> Read 4 bytes of data from DDR Memory
4500 ns, data read from DDR = h00000000
[4500] : *ZYNQ_VIP_INFO : Starting Address(0x20000004) -> Read 4 bytes of data from DDR Memory
4500 ns, data read from DDR = h01010101
[4500] : *ZYNQ_VIP_INFO : Starting Address(0x20000008) -> Read 4 bytes of data from DDR Memory
4500 ns, data read from DDR = h02020202

This is OK!