We are working on virtex 5 xc5vfx100t , we are trying to customize the board by selecting the proper processors and all. The board having the DDR part MT47H128M16RT-25E IT. But from the tool we are getting following DDRs,
a)DDR SDRAM MT46V16M16-5B b) DDR SDRAM MT46V16M16-5B_1 c) DDR2 SDRAM DIMM W1D32M72R8A-5A d) DDR2 SDRAM DIMM W1D32M72R8A-5A_1
we tried to match our part number with part(c)(DDR2 SDRAM DIMM W1D32M72R8A-5A) in ucf files but got some error as below.
ERROR:Place:1239 - A core generated by the Memory Interface Generator (MIG) has been detected in your design but not all of the corresponding IO are locked. All IO are required to be locked according to the MiG guidelines to ensure that proper timing can be met. Please review your user constraints file (*ucf) to ensure that all of these IO are locked. For more information on MIG IO placement rules, please see the Xilinx Memory Interface Generator (MIG) User Guide. The following IO are not locked: