UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
10,959 Views
Registered: ‎01-11-2014

DDR3_SDRAM initialization

Hi,

 

I am using DDR3 SDRAM in my system as data memory among other components, including a custom generated IP core which takes data from DDR3 through FSL. I am simulating the design and running for 5ms (simulation time). As it appears, there is no data on FSL bus from DDR3. How much time does it take for DDR3 initialization sequence to complete? I have got a message in console saying:

 

PHY_INIT: Memory Initialization completed at 7216926000

 

But I guess this refers to BRAM used by microblaze. Am I correct or it refers to DDR3? If it does, then why can't I see any data on data bus of either FSL or input to the IP core? (Possibility that I am monitoring a wrong signal!) 

 

I checked one post on this forum and it says it takes 500ms to run the initialization sequence for DDR. In that case its impossible to run simulation as 5ms itself takes around 17-18 hrs to complete. Is there any workaround, any way to tackle this problem? Is ther any way to make the DDR initialize quicker?

 

Thnaks, 

Ashutosh

Tags (2)
simulation output.png
0 Kudos
7 Replies
Xilinx Employee
Xilinx Employee
10,951 Views
Registered: ‎07-11-2011

Re: DDR3_SDRAM initialization

Hi,

 

In 7 series based on your memory configuration data width, single/multi controllers etc., , initialization  & calibration as a  whole can take up to 15-20 minutes of  your simulation time.

You can speed up this by setting SIM_BYPASS_INIT_CAL   = "FAST", unlike 6 series OFF is not supported so 7 series MIG takes considerable amount of time due to phasers which can't be bypassed even in simulation to have relaible data capture.

 

 

Hope this helps 

 

Regardd,

Vanitha. 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
10,945 Views
Registered: ‎01-11-2014

Re: DDR3_SDRAM initialization

Hi Vanitha,

 

Do you mean 15-20 min on simulation clock? Because, in that case, it is prohibitively slow and impossible to simulate!

 

Also, I think I am using 6 series. I am using Virtex 6 development board and the version for DDR3 says 

 

IP Type: mpmc

IP Version: 6.06.a

 

So, what approach do you suggest? If I use OFF, will DDR3 still work, as I need it to work to have data for energy profiling of the system. 

Also, where can I set this parameter SIM_BYPASS_INIT_CAL ?

 

Thanks,

Ashutosh

0 Kudos
10,943 Views
Registered: ‎01-11-2014

Re: DDR3_SDRAM initialization

I am using Xilinx ISE 14.2 and creating the system in XPS
0 Kudos
10,942 Views
Registered: ‎01-11-2014

Re: DDR3_SDRAM initialization

I found a document:

http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_92/ug406.pdf

 

It says if we set SIM_BYPASS_INIT_CAL  to fast, it will skip the initial 200us initialization delay. Does it mean it requires only 200us (simulation time) for initialization? In that case, I should eb able to see some activity on DDR after atleast 2-3 ms, right?

0 Kudos
Xilinx Employee
Xilinx Employee
10,940 Views
Registered: ‎07-11-2011

Re: DDR3_SDRAM initialization

Hi,

 

For V6 you can use "OFF" as well, it should be pretty quick, I have never waited for 2-3 ms

Can you check in standalone mode may be using MIG?

 

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
10,926 Views
Registered: ‎01-11-2014

Re: DDR3_SDRAM initialization

Where can I check that, and where can I set SIM_BYPASS_INIT_CAL value?

0 Kudos
Moderator
Moderator
10,845 Views
Registered: ‎04-17-2011

Re: DDR3_SDRAM initialization

Open sim_tb_top and search SIM_BYPASS_INIT_CAL and change it to "OFF"
Page 97: http://www.xilinx.com/support/documentation/ip_documentation/ug586_7Series_MIS.pdf
Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos