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Newbie
Newbie
5,585 Views
Registered: ‎04-15-2016

DDR4 Read Sample Issue in VCS Simulation

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I using the Ultrascale v1_1 DDR4 Controller and Phy in a VCS simulation with Denali DDR4-1600 Memory Models.

The sampling of the DQS lines in ddr4_phy_v1_1_xiphy_behav.sv misses the DQS pulses. This block uses a

delayed clock, o_clk_rd, to sample the DQS signals. I had to add an additional 100ps delay to this clock to

capture the DQS signals correctly.

Is there some external parameter that I should be adjusting rather than having to edit the verilog?

 

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Xilinx Employee
Xilinx Employee
10,149 Views
Registered: ‎07-11-2011

Re: DDR4 Read Sample Issue in VCS Simulation

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@wtesling

 

Denali memory models are not officially supported by Xilinx, so please use Micron or vendor specific memory model for simulations.

If you still need MIG support with Denali models I would suggest you to contact your local FAE.

 

Hope this helps

 

-Vanitha

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Highlighted
Xilinx Employee
Xilinx Employee
10,150 Views
Registered: ‎07-11-2011

Re: DDR4 Read Sample Issue in VCS Simulation

Jump to solution

@wtesling

 

Denali memory models are not officially supported by Xilinx, so please use Micron or vendor specific memory model for simulations.

If you still need MIG support with Denali models I would suggest you to contact your local FAE.

 

Hope this helps

 

-Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

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