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Anonymous
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DDR4 simulation not working with ddr4_0_sim_netlist.v

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Hi all,

 

I have a project in Vivado 2017.1. FPGA is Kintex Ultra-scale.

I created  DDR4 IP in the project, opened example design and simulated. Simulation worked well and test passed successfully.

 

Then I created anothe project with  ddr4_0_sim_netlist.v. ( I have also added the remaining files example_top.sv, ddr4_v2_2_axi_tg_top.sv, sim_tb_top.sv etc) .

But this time simulation did not work well. MIG do not perform any transaction (cs_n & reset_n to memory model are LOW).

 

What may be the issue? 

 

Regards

Anoop

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vemulad
Xilinx Employee
Xilinx Employee
2,580 Views
Registered: ‎09-20-2012

Hi @Anonymous

 

No, *_sim_netlist.v  is post synthesis simulation netlist. To run the behavioral simulation you need to add the files listed in the simulation scripts located in .ip_user_files\sim_scripts\<ip_name>\xsim

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
2,027 Views
Registered: ‎09-20-2012

Hi @Anonymous

 

ddr4_0_sim_netlist.v is structural netlist file. We support only behavioral simulation with MIG.

 

You can look at the example design simulation scripts (use export_simulation command) to know the list of IP files used for simulation. 

Thanks,
Deepika.
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Anonymous
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Hi 

 

Thank for your reply.

I am doing behavioral simulation of MIG only( with example_top and sim_tb_top).

As my understanding, for all Xilinx IPs which use .xci in project , *_sim_netlist.v can be used in behavioral simulation mimicking the IP. Please correct me if I am wrong.

 

Regards

Anoop

 

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vemulad
Xilinx Employee
Xilinx Employee
2,581 Views
Registered: ‎09-20-2012

Hi @Anonymous

 

No, *_sim_netlist.v  is post synthesis simulation netlist. To run the behavioral simulation you need to add the files listed in the simulation scripts located in .ip_user_files\sim_scripts\<ip_name>\xsim

Thanks,
Deepika.
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Anonymous
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Hi 

 

 

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vemulad
Xilinx Employee
Xilinx Employee
2,003 Views
Registered: ‎09-20-2012

Hi @Anonymous

 

If you use .XCI file, the tool will automatically read all the files needed for simulation.

 

You have to include the memory model file separately for MIG.

Thanks,
Deepika.
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sandkumc663
Observer
Observer
697 Views
Registered: ‎07-15-2019

Hi

I have one query related to this topic. Is there any way to simulate with ddr4*_sim_netlist?

Thanks

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