DDR4 simulation not working with ddr4_0_sim_netlist.v

[Anonymous]

Hi all,

I have a project in Vivado 2017.1. FPGA is Kintex Ultra-scale.

I created  DDR4 IP in the project, opened example design and simulated. Simulation worked well and test passed successfully.

Then I created anothe project with  ddr4_0_sim_netlist.v. ( I have also added the remaining files example_top.sv, ddr4_v2_2_axi_tg_top.sv, sim_tb_top.sv etc) .

But this time simulation did not work well. MIG do not perform any transaction (cs_n & reset_n to memory model are LOW).

What may be the issue? 

Regards

Anoop

[vemulad]

Hi @Anonymous

ddr4_0_sim_netlist.v is structural netlist file. We support only behavioral simulation with MIG.

You can look at the example design simulation scripts (use export_simulation command) to know the list of IP files used for simulation. 

[Anonymous]

Hi vemulad

Thank for your reply.

I am doing behavioral simulation of MIG only( with example_top and sim_tb_top).

As my understanding, for all Xilinx IPs which use .xci in project , *_sim_netlist.v can be used in behavioral simulation mimicking the IP. Please correct me if I am wrong.

Regards

Anoop

[vemulad · Accepted solution]

Hi @Anonymous

No, *_sim_netlist.v  is post synthesis simulation netlist. To run the behavioral simulation you need to add the files listed in the simulation scripts located in .ip_user_files\sim_scripts\<ip_name>\xsim

[Anonymous]

Hi vemulad,

Thanks. It clarifies. 

So in order to perform behavioral simulation of MIG, I need to use either ddr4_0.xci or the .sv files generated from it. Am I correct?

Regards

Anoop

[vemulad]

Hi @Anonymous

If you use .XCI file, the tool will automatically read all the files needed for simulation.

You have to include the memory model file separately for MIG.

[sandkumc663]

Hi

I have one query related to this topic. Is there any way to simulate with ddr4*_sim_netlist?

Thanks