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Anonymous
Not applicable
4,319 Views

Data type error

I am having problems with a test bench file. I am getting the following errors-

# ** Error: C:/Documents and Settings/hitheshn/Desktop/Second_actel/stimulus/my_timer1_tbench.vhd(179): Signal "mmin" is type std.standard.integer; expecting type ieee.std_logic_1164.std_logic_vector.
# ** Error: C:/Documents and Settings/hitheshn/Desktop/Second_actel/stimulus/my_timer1_tbench.vhd(180): Signal "ssec" is type std.standard.integer; expecting type ieee.std_logic_1164.std_logic_vector.
# ** Error: C:/Documents and Settings/hitheshn/Desktop/Second_actel/stimulus/my_timer1_tbench.vhd(183): VHDL Compiler exiting
# ** Error: C:/Actel/Libero_v8.5/Model/win32acoem/vcom failed.

 

The vhd file was generated from a waveform. Not sure how to solve this error.

Any help would be great!

 

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Xilinx Employee
Xilinx Employee
4,302 Views
Registered: ‎08-15-2007

Re: Data type error

Hello,

 

Check your signal types and assignments.  It appears signals "mmin" and "ssec" have been declared as std_logic_vector, and not integer.  Meaning, you cannot assign integers to these signals, but only a vector of bits (i.e. "00010010").

 

 

Eddie
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