06-18-2018 08:55 PM
I can single step through systemverilog classes in Vivado, however I can find no way to inspect local or member variables whilst I'm doing it. The 'scope' page shows only real signals, I've pulled up the 'locals', 'objects', 'stacks' and 'frames' windows but every one of those is empty when stopped at a breakpoint in a class method. I tried changing the --debug argument to 'all' and 'subprogram' but that didn't help and I've looked at some of the TCL commands available when running the sim but haven't found one which helps.
I can't work out what the 'local' and 'object' windows are for if they don't show locals and objects, is there another flag I need to add somewhere, are there some simulator TCL commands I need to know or does the simulator not support printing out class values during debugging?
06-18-2018 09:26 PM
06-18-2018 09:50 PM
ok that works for any instantiated modules/interfaces etc, but those are the same things I can show in the wave window eg
top is the top module, link is an instantiated module, and RESET is a signal
However I can't find ANY path which gives me access to instantiated objects of systemverilog classes, which are the things I can't show in the wave window because they don't show up in scope or objects or locals or anywhere. That's what I'm trying to debug.
So if, in my 'top' module I have a variable of type TestTX which I've made like this
test_tx = new
what hierarchical_scope_signal path can I use to get its value (or the value of its class members).
06-18-2018 11:09 PM
2018.1 on Linux
ok i just put together a trivial do-nothing example, attached, just start a new project and import this as the only source file.
So the question is how do you debug the class Foo and the instance my_foo. For instance I can put a breakpoint on line 22 (this.do_something(bar+1)) and the simulation stops there but I can't find any way to get the value of bar, or this or anything. Can't get_value() it, can't find it in the Scope, it's not in Objects, it's not in Locals.
I can breakpoint at line 61 or somewhere around there, my_foo exists at that point, but there's no way to show it, it doesn't appear in locals (even though it's a local), I can't find a way to display its value with get_value as you suggested earlier. eg
get_value /top/my_foo ..
doesn't work. Nor does any other path I can think of.
I can graph the signals, I can see the module (top) and the interface (my_i1), that's all fine, but the instantiated Foo, can't debug it (except with $display and that doesn't count as proper debugging)
So - again - how do you debug instances of systemverilog classes in vivado, or can't you?
Note I had to attach the file as testbench.txt and not testbench.sv as the website rejects the file otherwise.
03-26-2020 05:44 PM
Did you ever find out if you could get visibility of classes and their variables?
I suspect not. Even Vivado 2019.2's XSIM doesn't have visibility of local variables declared inside always blocks in Verilog/SV yet (unlike Modelsim).
01-13-2021 08:29 AM
Don't hold your breath on this being answered. Unless you get a quick easy answer from a Xilinx employee or an expert is interested in your subject.
Meanwhile I found the article titled "Better Living Through Better Class-Based SystemVerilog Debug" on page 54 of this link..
...it goes to show that debugging class based code isn't that easy and shows a few techniques for doing it although it leans towards UVM.
I would be interested if there is any more information on performing this with Vivado's XSIM. I tried 2020.2 but it's no better and has it's own set of problems.