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flydrive
Observer
Observer
1,686 Views
Registered: ‎09-10-2016

Debugging systemverilog classes with Vivado

I can single step through systemverilog classes in Vivado, however I can find no way to inspect local or member variables whilst I'm doing it. The 'scope' page shows only real signals, I've pulled up the 'locals', 'objects', 'stacks' and 'frames' windows but every one of those is empty when stopped at a breakpoint in a class method. I tried changing the --debug argument to 'all' and 'subprogram' but that didn't help and I've looked at some of the TCL commands available when running the sim but haven't found one which helps. 

 

I can't work out what the 'local' and 'object' windows are for if they don't show locals and objects, is there another flag I need to add somewhere, are there some simulator TCL commands I need to know or does the simulator not support printing out class values during debugging? 

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7 Replies
sunilku
Xilinx Employee
Xilinx Employee
1,672 Views
Registered: ‎08-10-2015

Hi @flydrive,

 

 

You can use get_value TCL command to display the values in tcl console.

Syntax: get_value <hierarchical_scope_signal>

 

 

Thanks,

Sunilkumar

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flydrive
Observer
Observer
1,662 Views
Registered: ‎09-10-2016

 

ok that works for any instantiated modules/interfaces etc, but those are the same things I can show in the wave window eg

 

get_value /top/link/RESET

 

top is the top module, link is an instantiated module, and RESET is a signal

 

However I can't find ANY path which gives me access to instantiated objects of systemverilog classes, which are the things I can't show in the wave window because they don't show up in scope or objects or locals or anywhere. That's what I'm trying to debug. 

 

So if, in my 'top' module I have a variable of type TestTX which I've made like this

 

initial begin 

 .....

    TestTX test_tx;

    test_tx = new

....

 

what hierarchical_scope_signal path can I use to get its value (or the value of its class members). 

 

 

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sunilku
Xilinx Employee
Xilinx Employee
1,650 Views
Registered: ‎08-10-2015

hi @flydrive,

 

Can you please share design files, Vivado version and platform details??/

 

 

 

Thanks,

Sunilkumar

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flydrive
Observer
Observer
1,639 Views
Registered: ‎09-10-2016

2018.1 on Linux

 

ok i just put together a trivial do-nothing example, attached, just start a new project and import this as the only source file. 

 

So the question is how do you debug the class Foo and the instance my_foo. For instance I can put a breakpoint on line 22 (this.do_something(bar+1)) and the simulation stops there but I can't find any way to get the value of bar, or this or anything. Can't get_value() it, can't find it in the Scope, it's not in Objects, it's not in Locals. 

 

I can breakpoint at line 61 or somewhere around there, my_foo exists at that point, but there's no way to show it, it doesn't appear in locals (even though it's a local), I can't find a way to display its value with get_value as you suggested earlier. eg

 

 

get_value /top/my_foo ..

 

doesn't work. Nor does any other path I can think of. 

 

I can graph the signals, I can see the module (top) and the interface (my_i1), that's all fine, but the instantiated Foo, can't debug it (except with $display and that doesn't count as proper debugging)

 

So - again - how do you debug instances of systemverilog classes in vivado, or can't you? 

 

Note I had to attach the file as testbench.txt and not testbench.sv as the website rejects the file otherwise. 

 

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steve_farmer
Adventurer
Adventurer
795 Views
Registered: ‎06-25-2014

Did you ever find out if you could get visibility of classes and their variables?

I suspect not. Even Vivado 2019.2's XSIM doesn't have visibility of local variables declared inside always blocks in Verilog/SV yet (unlike Modelsim).

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choksiv
Observer
Observer
384 Views
Registered: ‎06-27-2019

Was this issue ever addressed? I never find Xilinx Tech support people responding/addressing the real questions. This is sad.

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steve_farmer
Adventurer
Adventurer
355 Views
Registered: ‎06-25-2014

Don't hold your breath on this being answered. Unless you get a quick easy answer from a Xilinx employee or an expert is interested in your subject.

Meanwhile I found the article titled "Better Living Through Better Class-Based SystemVerilog Debug" on page 54 of this link..

http://verificationhorizons.verificationacademy.com/volume-8_issue-2/complete-issue/stream/volume8-issue2-verification-horizons-publication-lr.pdf

...it goes to show that debugging class based code isn't that easy and shows a few techniques for doing it although it leans towards UVM.

I would be interested if there is any more information on performing this with Vivado's XSIM. I tried 2020.2 but it's no better and has it's own set of problems.