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Visitor
Visitor
9,257 Views
Registered: ‎07-25-2011

Delay a Clock Signal without Violating Constraints

The snippet below is an attempt to delay the square wave ph1 by three clocks of hsclock.  It appears to work in my iVerilog simulator and it builds in ise but when I program it into a coolrunner part, ph2 just remains a zero level. 

 

Notes:

    ph1 and ph2 are one bit rigisters

    delay_ctr is a n eight bit counter

    hsclock is approximately eight times as fast as ph1 and not coherent with it

 

    always @(ph1)
    begin
        delay_ctr <= 0 ;
    end
    
    always @(hsclk)
    begin
        delay_ctr <= delay_ctr + 1 ;
        if(delay_ctr == 3)
        begin
            ph2 <= ph1 ;
        end
    end

 

I believe I have violated a Verilog restriction of changing the counter register in two different always loops but, as I said, it works in the simulator and it builds with ise without errors.

 

Can anyone suggest a  way to accomplish the required delay function without violating the rule of not controlling a register in two different always loops?

 

Thanks

 

John Battle

jobattle@caltech.edu

 

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Xilinx Employee
Xilinx Employee
9,241 Views
Registered: ‎07-31-2012

Re: Delay a Clock Signal without Violating Constraints

Hi,

 

Are you checking in behavioral simulation or post fit simulation.?

 

Check post fit simulation for correct results.

 

Give timing constrainnts in your design and check.

Thanks,
Anirudh

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Professor
Professor
9,233 Views
Registered: ‎08-14-2007

Re: Delay a Clock Signal without Violating Constraints

You might want to check the post-fit equations in the report.  I'm pretty sure that if you really wanted to use both edges of hsclk, you need to do that by writing:

 

always @ (posedge hsclk or negedge hsclk) 

 

By the way this only works in CR2, not other Xilinx families, and only because of the clock doubling feature of CR2.

 

My guess is that synthesis has just ignored the sensitivity list and tried to build something combinatorial.

 

Anyway, I'd suggest using a delay line (shift register) rather than the counter approach.  For a delay of 3 it works out to the same number of flip-flops.

 

And in any case you don't want to assign the same signal in two always blocks.  I'm not sure why synthesis did not flag this as a "multi-source" error.

-- Gabor
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Xilinx Employee
Xilinx Employee
9,216 Views
Registered: ‎07-31-2012

Re: Delay a Clock Signal without Violating Constraints

Hi,

 

As you rightly pointed out, you need to give an intial statement for initializing the dealy_ctr. Also for the 2nd always block give a edge triggered loigc (posedge, negedge). Also instead of using an increment logic, you can delay it using 3 registers. 

 

Try these options and check if it works now.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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