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Adventurer
Adventurer
9,552 Views
Registered: ‎07-30-2013

Delayline Timing Simulation

Hi,

 

I try to simulate the delayline make up by a carry4 primitive.  I built and implemented a simple one but simulation show that all the taps turn on at the same time (effectively no delay) when a step is applied at the signal input.  I would appreciate for any idea to fix the simulation.

 

Block Diagram:

 

delayline.PNG

Post Implementation Simulation:

post_imp_sim.PNG

 

I have attached the project if some one what run it.

 

Thanks

Henry

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16 Replies
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Moderator
Moderator
9,541 Views
Registered: ‎07-01-2015

Re: Delayline Timing Simulation

Hi @hyleung,

 

Please attach delayline.v and delayline_tb.v here. 

 

Thanks,
Arpan

Thanks,
Arpan
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Xilinx Employee
Xilinx Employee
9,530 Views
Registered: ‎05-07-2015

Re: Delayline Timing Simulation

HI @hyleung

 

Are you sure  it is a post implementation timing simulation?

Also, when you attach any project . Go to File --> Archive Project and send the created archive.(.zip file)

Thanks
Bharath
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Moderator
Moderator
9,517 Views
Registered: ‎01-16-2013

Re: Delayline Timing Simulation

Hi,

 

From the snapshot this won't looklike post-impl timing simulation.

 

As Bharath suggested check once again.

 

Also include 100ns of delay before start the stimulus. 100ns is required to satisfy the GSR (Global Set Reset).

 

Thanks,
Yash

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Moderator
Moderator
9,509 Views
Registered: ‎04-17-2011

Re: Delayline Timing Simulation

I beleive you are running a Timing Simulation. Made the same project as yours and ran Timing Simulation (Post-Implementaion) and can see the timing working properly:

delay.JPG

I have attached my project archive for your reference. Vivado 2015.2.

Regards,
Debraj
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Adventurer
Adventurer
9,489 Views
Registered: ‎07-30-2013

Re: Delayline Timing Simulation

The source file is included in:

\delayline_test.xpr\delayline_test\delayline_test.srcs\sources_1\new

\delayline_test.xpr\delayline_test\delayline_test.srcs\sim_1\new and

\delayline_test.xpr\delayline_test\delayline_test.srcs\constrs_1\new

 

I re-attached these files here anyway.

 

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Adventurer
Adventurer
9,483 Views
Registered: ‎07-30-2013

Re: Delayline Timing Simulation

Hi Debraj,

 

Thanks for your project.  Unfortunately, I can't open your project because I am constrainted to Vivado 2014.2.  I have import your code but does not see any delay in post-imp simulation.  I am wondering if you can port your project into 2014.2?

 

Thanks

Henry

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Adventurer
Adventurer
9,481 Views
Registered: ‎07-30-2013

Re: Delayline Timing Simulation

Yes, I am pretty sure it is post-imp timing simulation.

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Adventurer
Adventurer
9,480 Views
Registered: ‎07-30-2013

Re: Delayline Timing Simulation

Thanks for your reply.  I have try adding 100ns delay but doesn't make any different.

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Moderator
Moderator
9,462 Views
Registered: ‎07-01-2015

Re: Delayline Timing Simulation

Hi @hyleung,

 

I tried with your code only. 

It's working at my end with post implementation timing simulation.

The only concern I have it I think you have not zoomed the signal view properly.

 

Please try the following steps and let us know the outcomes:

  • Implement design
  • Run Post-implementation timing simulation
  • Keep the cursor on rising edge of tap[1] signal and zoom it. 

Attaching snapshot of testbench for your reference.

 

Thanks,
Arpan

 

Thanks,
Arpan
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Adventurer
Adventurer
9,155 Views
Registered: ‎07-30-2013

Re: Delayline Timing Simulation

I have rebuilt the project in Vivado 2013.3 and delays appeared at the outputs.  It seems that it is related to the 2014.2.  Is there anybody notice post-imp timing simulation issue with this version?

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Adventurer
Adventurer
9,151 Views
Registered: ‎07-30-2013

Re: Delayline Timing Simulation

Hi Arpan,

 

Which version of vivado you used in the simulation?  I have the delay simulated in 2013.3 but not 2014.2.

 

Henry

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Moderator
Moderator
9,144 Views
Registered: ‎07-01-2015

Re: Delayline Timing Simulation

Hi @hyleung,

 

I used Vivado 2015.3.

 

Which device and package you are using?

 

Thanks,
Arpan

Thanks,
Arpan
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Adventurer
Adventurer
9,138 Views
Registered: ‎07-30-2013

Re: Delayline Timing Simulation

It is an experimental design.  For now, I targeted it for the K7 on the KC705 board.

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Explorer
Explorer
9,127 Views
Registered: ‎04-28-2015

Re: Delayline Timing Simulation

HI,

If possible, do consider upgrading to latest version of Vivado.
This will ensure better results as many bugs get fixed along the process.

Regards,
Tushar
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Moderator
Moderator
9,121 Views
Registered: ‎07-01-2015

Re: Delayline Timing Simulation

Hi @hyleung,

 

As your design is working with 2013.3 either use 2013.3 else I would suggest you to use VIvado latest version.

 

Thanks,
Arpan

Thanks,
Arpan
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Adventurer
Adventurer
9,104 Views
Registered: ‎07-30-2013

Re: Delayline Timing Simulation

Thanks everyone for the time on this issue.  I think I will go with the lastest vivado.

 

Henry

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