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9,540 Views
Registered: ‎09-19-2014

Design and Simulation of FFT and IFFT using FPGA Implementation

Hi,

I am working on FFT implementation using VHDL.I have done with the code but i am not getting how to give input when going for  simulation.I have to give any number as an input.So,what should i do for simulation?

Please reply fast.

Regards,

Urvi

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3 Replies
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Xilinx Employee
Xilinx Employee
9,527 Views
Registered: ‎09-13-2014

Re: Design and Simulation of FFT and IFFT using FPGA Implementation

Hi,

 

Regarding giving input to your design for simulation, you need to write a test bench. The test bench can be either in verilog or VHDL as vivado simulator supports MIX design. In test bench, you need to instantiate your FFT design and in port connection, you can provide any number as input through signal/variable.

 

Say for example I have a dummy design DUT which look like

 

entity DUT is

    port(in1 : in std_logic; out1 : out std_logic);

end entity DUT;

 

architecture arch of DUT is

begin

...

end architecture arch;

 

Now if I want to drive some value to the input, I can write a test bench say tb.v

 

module tb;

reg in1; // reg as input to DUT is 1 bit wide, if in1 is vector in DUT then declaration can be like reg [3:0] in1; where 3:0 is vector size in DUT side

wire out1;

 

DUT I1(in1, out1);

 

initial

begin

    in1 = 0;

   forever #2 in1 = ~in1;

end

 

initial #1000 $finish;

endmodule

 

Now you need to as this 'tb.v' file in your project as simulation source file so that it don't be the part for synthesis.

 

Hope this may resolve your query. Please let us know if you are looking for anything else.

 

--dhiRAj

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9,508 Views
Registered: ‎09-19-2014

Re: Design and Simulation of FFT and IFFT using FPGA Implementation

I've written this test bench:

 

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS
signal x,y : comp_array;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: entity work.fft4 PORT MAP (
x => x,
y => y
);

-- Stimulus process
stim_proc: process
begin
--sample inputs in time domain.
x(0) <= (-2.0,1.2);
x(1) <= (-2.2,1.7);
x(2) <= (1.0,-2.0);
x(3) <= (-3.0,-3.2);

wait;
end process;

END;

 

But what should I give input at test bench waveforms.I am attaching one screenshot so that you will be able to understand.

 

simulation.png
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Xilinx Employee
Xilinx Employee
9,494 Views
Registered: ‎08-02-2011

Re: Design and Simulation of FFT and IFFT using FPGA Implementation

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