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Adventurer
Adventurer
9,090 Views
Registered: ‎05-06-2012

Design simulation error

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 Hai,

 

 

      My desige consists of IP core(fixed to float) generated in VIVADO. While simulating this design in Model simulator i am getting following error,

 

 

** Error: D:/DBF_NSTL/IIR_simulation/IIR_Fiter_simulation_K7_modelsim/sub.vhd(56): Library floating_point_v7_0 not found.
** Error: D:/DBF_NSTL/IIR_simulation/IIR_Fiter_simulation_K7_modelsim/sub.vhd(57): (vcom-1136) Unknown identifier "floating_point_v7_0".
** Error: D:/DBF_NSTL/IIR_simulation/IIR_Fiter_simulation_K7_modelsim/sub.vhd(59): VHDL Compiler exiting

 

 

how to over come this.

 

 

  In old version of IP, the Xilinx have used Library XilinxCoreLib;

theertha
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1 Solution

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Moderator
Moderator
10,718 Views
Registered: ‎04-17-2011

Re: Design simulation error

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Questasim is an advanced version of Modelsim with added Verification and Code Coverage features but the GUI and commands are same. You would not find any difference in the cockpit for both the tools . Feel free to use any one of them.
Regards,
Debraj
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12 Replies
Moderator
Moderator
9,081 Views
Registered: ‎06-05-2013

Re: Design simulation error

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To resolve this issue, recompile the libraries using compxlib. Check the following thread http://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-and-ISE-simulation-libraries-compatible/td-p/336003
Regards,
Harry
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Xilinx Employee
Xilinx Employee
9,081 Views
Registered: ‎09-20-2012

Re: Design simulation error

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Hi,

 

There is no Xilinxcorelib in vivado.

 

Simulation models of Xilinx Vivado IP cores are delivered as an output product when the IP is generated. 

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
9,076 Views
Registered: ‎07-16-2008

Re: Design simulation error

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In Vivado, the files IP delivered ususally bond to specific libraries.

I'd suggest that you launch Modelsim from Vivado so that the correct simulaiton script (.do) can be generated for you.

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Xilinx Employee
Xilinx Employee
9,076 Views
Registered: ‎10-24-2013

Re: Design simulation error

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Use the following tcl command compile_simlib -help in the vivado tcl console for help on generating compiled libraries.
Thanks,Vijay
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Xilinx Employee
Xilinx Employee
9,068 Views
Registered: ‎09-20-2012

Re: Design simulation error

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To add to what Grace mentioned, you can refer to chapter-7 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug900-vivado-logic-simulation.pdf for details on simulation with modelsim.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Adventurer
Adventurer
9,061 Views
Registered: ‎05-06-2012

Re: Design simulation error

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Hai,

 

   i launched Modelsim from Vivado. still i am getting error message

 

# ** Error: d:/DBF_NSTL/DBF_DESIGN_VIVADO/IIR_Filter_simulation/IIR_Simulation/IIR_Simulation.srcs/sources_1/ip/multiplier2/xbip_utils_v3_0/hdl/xbip_utils_v3_0_pkg.vhd(1): near "protect":
# ** Error: d:/DBF_NSTL/DBF_DESIGN_VIVADO/IIR_Filter_simulation/IIR_Simulation/IIR_Simulation.srcs/sources_1/ip/multiplier2/xbip_utils_v3_0/hdl/xbip_utils_v3_0_pkg.vhd(1): VHDL Compiler exiting
# ** Error: C:/Modeltech_6.3f/win32/vcom failed.

theertha
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Xilinx Employee
Xilinx Employee
9,056 Views
Registered: ‎09-20-2012

Re: Design simulation error

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Hi,

 

Are you using supported modelsim version (10.2a)?

 

Check the release notes page-11 for supported simulators http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug973-vivado-release-notes-install-license.pdf

 

Thanks,

Deepika.

Thanks,
Deepika.
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Adventurer
Adventurer
9,044 Views
Registered: ‎05-06-2012

Re: Design simulation error

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Hai,

 

   I have gone through page no. 11. But in that model sim is not mentioned

theertha
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Xilinx Employee
Xilinx Employee
9,044 Views
Registered: ‎09-20-2012

Re: Design simulation error

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Hi,

 

Modelsim supported version is same as Questa supported version which is 10.2a for vivado 2013.4.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Adventurer
Adventurer
5,585 Views
Registered: ‎05-06-2012

Re: Design simulation error

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Hai,

 

    Now i am using ModelsSim SE PLUS 6.3f. So since i am using Vivado, I have tto use Questa  10.2a .Is questa will be same as model sim? (I have not used questa)

theertha
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Xilinx Employee
Xilinx Employee
5,579 Views
Registered: ‎09-20-2012

Re: Design simulation error

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Hi,

 

You can use Questasim 10.2a or above (or) Modelsim 10.2a or above.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Moderator
Moderator
10,719 Views
Registered: ‎04-17-2011

Re: Design simulation error

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Questasim is an advanced version of Modelsim with added Verification and Code Coverage features but the GUI and commands are same. You would not find any difference in the cockpit for both the tools . Feel free to use any one of them.
Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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