08-01-2019 06:33 AM
This is not a too serious problem more like fun to know.
I'm looking for a way to detect whether an interpreter understands VHDL-2008 or basic VHDL-1993. The code must be VHDL-1993 but must produce a different result depending on the VHDL-2008 capabillity of the compiler/simulator.
Something similar to this:
function is_sim return boolean is variable result : boolean; begin result := false; -- synthesis translate_off result := true; -- synthesis translate_on return result; end function is_sim;
this just returns true if simulation and false if synthesis.
Can such a thing exist?
08-01-2019 07:24 AM - edited 08-01-2019 07:26 AM
Short answer is No. I also dont know any tool that would do this (it will just throw syntax errors if you try and compile VHDL 2008 code in VHDL 93 mode)
VHDL 2019 does add some interesting features, like access to environmental variables and some pre-defined environmental variables:
impure function VHDL_VERSION return string ; function TOOL_TYPE return string ; function TOOL_VENDOR return string ; function TOOL_NAME return string ; function TOOL_EDITION return string ; function TOOL_VERSION return string ;
But dont expect any Xilinx support any time soon (they're still trying to implement 2008).
Link to all VHDL 2019 Features:
08-05-2019 06:19 AM
I also believe the answer is no. Unless there's some trick or bug in the implementation (feature) that would enable a function to return something unexpected under VHDL-93. Because the code must be VHDL-93 compliant as you also pointed out, it must be able to run in an VHDL-93 environment just checking if the simulator supports VHDL-2008 and return another result in this case.
Yeah, VHDL-2019 will probably not be implemented in Vivado the next 20 years if ever.
08-05-2019 11:32 AM