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s96971
Observer
Observer
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Registered: ‎09-27-2017

Differents between various schematic in Vivado.

Hello,I'm new in this ambient.I saw that Vivado have various type of schematics:there's schematic in RTL analysis,schematic in synthesis and schematic in implementation.Can you say to me the differents between this schematics?I'd like to know because in a scheme some pins are connected,in others the same are not connected.I defined connections in xdc file of my device (Arty).

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borisq
Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

the 3 schematics show the netlist or connections in different stage.

First in RTL, second after synthesis and the third after implemention (place and route)

Regarding pins connection, you can put some snapshots.

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s96971
Observer
Observer
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Registered: ‎09-27-2017

Here the screenshots,first RTL,second synthesis..As you can saw,in the first,at left,the pin rx_in[0:0] is connected,while in the second the same is not connected.I also noted that circuits are bit different and FIFO00 have less pins.Why?

Thanks!

RTL.png
Sintesi.png
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hemangd
Moderator
Moderator
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Registered: ‎03-16-2017

Hi @s96971,

 

Can you share the synthesized log file (runme.log) from your project directory? It will be stored in synth_1 directory. 

 

Maybe tool is doing optimization with rx00 module while synthesis.  

 

Regards,

hemangd

Regards,
hemangd

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amaccre
Moderator
Moderator
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Registered: ‎04-24-2013

Hi @s96971,

 

The elaborated design schematic shows the connections as you have coded them in RTL.

 

The Synthesised design schematic shows the design as it has been built out of the primitives for the device that you are targeting.

 

However looking at your Synthesised schematic it looks as if there is more going on. The rx_out, rx_outclock etc are all grounded.

 

At a guess I would suggest that you have possibly done something incorrect with a clock. This will mean that the design will never change state. And since the primitives usually come up (unless specified otherwise) with a default value of 0, then all the unneeded design is optimised away and the outputs are set to 0.

 

I would check that you don't have a clock input connected to ground as somewhere to start.

Best Regards
Aidan

 

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s96971
Observer
Observer
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Registered: ‎09-27-2017

Here the file .thanks for help.Before to continue to my work I want be sure to understand how Vivado work in this case.

 

 

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amaccre
Moderator
Moderator
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Registered: ‎04-24-2013

Hi @s96971,

 

Looking at the log file, the reason that part of the design is being optimised away is that latches are being inferred and the enable of the latches is always disabled. You can see this on lines 175-184 and from line 294 onwards.

 

In an FPGA, you typically want your logic to be fully synchronous having all storage elements (like FF's) clocked from a single clock source.

 

Was the source for this project a netlist that was synthesised for a different device?

 

Best Regards
Aidan

 

PS: If you include the @ symbol before the persons name then they are notified that you have replied.

 

 

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s96971
Observer
Observer
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Registered: ‎09-27-2017

Hello @amaccrethanks for help.

This is an old core https://opencores.org/project/ethernet_tri_mode/overview made for Modelsim.the author not specified clearly what he used to put to FPGA; my thesis work is use this core in Vivado and Arty board for a simple data transfer system,similar to ethernet but more simple.

So my actual work is interface this of the old core

 

module altcdr_rx (
    rx_in,        // required port, data input
    rx_inclock,   // required port, input reference clock
    rx_coreclock, // required port, core clock
    rx_aclr,      // asynchronous reset for the RX and FIFO
    rx_pll_aclr,  // asynchronous reset for the PLL
    rx_fifo_rden, // FIFO read enable
    rx_out,       // data output
    rx_outclock,  // global clock recovered from channel 0
    rx_pll_locked,// PLL lock signal
    rx_locklost,  // RX lock of lost wrt input data
    rx_rlv,       // data run length violation flag
    rx_full,      // FIFO full signal
    rx_empty,     // FIFO empty signal
    rx_rec_clk    // recovered clock from each channel
);

 

with

https://github.com/Digilent/Arty/blob/master/Resources/XDC/Arty_Master.xdc

 

on ethernet phy (is Arty pin scheme)

 

 

I thinked these connections

 

rx_fifo_rden[0]        H15
rx_out[2:0]              D18,E17,E18
rx_locklost[0]          C17
rx_rlv[0]                   G14
rx_full[0]                  H14
rx_empty[0]            J14
rx_rec_clk[0]           H17
rx_inclk                    H16
rx_coreclock[0]      E3,periodo 12,5
rx_aclr                     C16
rx_outclock             F15
rx_pll_locked          J13

 

 

rx_in                        G17
rx_pll_aclr              G16

 

but as you suggest me,I must analyze clocks better,to get work.

What do you think of my connections?

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s96971
Observer
Observer
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Registered: ‎09-27-2017

Hello @amaccre,@ I examinated my project and noted that clk0 of my pll is not connect to rx_0x (see my 2 screnshots here):in effecty I don't specify it in xdc file,but rx_inclock is connect directly to clk of pll (in syntetized design).

Must I connect directly in someway?If I correctly understand,is the tool that generate connections,so I must modify something,I saw the clocks and for me seems ok (but I'm newby,so I'm not sure)

In my last post I write the connection,here there's the original xdc file.

 

https://github.com/Digilent/Arty/blob/master/Resources/XDC/Arty_Master.xdc

Thanks for help!

 

 

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amaccre
Moderator
Moderator
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Registered: ‎04-24-2013

Hi @s96971,

 

Would it be possible for you to share the project and I can take a look at it?

If you don't wish to post it here then let me know and I can send you a link to transfer it securely.

Best Regards
Aidan

 

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s96971
Observer
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Registered: ‎09-27-2017

@amaccreHere my project.It's a zip archive with password.I'll send you password by private message here.After extract,go to Tesi_progetto folder,then Tesi_progetto folder another time and open Tesi_progetto.xpr file.

Thanks!!!

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amaccre
Moderator
Moderator
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Registered: ‎04-24-2013

Hi @s96971,

 

Thank you for the files, looking at you design I noticed a few issues.

 

In the Elaborated design the rx01 - 17 have their datain grounded and so will never change, also the fifo01 - 17 have no output so they provide no use to the design. This is why they are optimised away during synthesis.

 

Elaborated.JPG

 

rx00 and fifo00 are a different story.

 

If you look at the data path through rx00, it looks ok at first glance but it provides no output to fifo00 which is why it is being optimised away. Looking in the synthesis log it has the following warnings.

 

WARNING: [Synth 8-264] enable of latch \rx00/deser_data_arr_reg[0] is always disabled
WARNING: [Synth 8-264] enable of latch \rx00/deser_data_arr_reg[1] is always disabled
WARNING: [Synth 8-264] enable of latch \rx00/deser_data_arr_reg[2] is always disabled

 

Digging into this you can see that the data path and the enable for the latch.

 

DataPath.JPG

 

The enable for the latch is controlled by the AND gate dataout_tmp_i, but this gate can never go high due to the connections on rlv_set1_i. This is checking that the two inputs are not equal, but they are tied together.

 

This maps to line 17870 of the code:

 if ((clk_in === 1'b1) && (clk_last_value !== clk_in))

 

You can see this by highlighting the element in the schematic and clicking F7 to show the code. (or by right clicking)

 

Best Regards
Aidan

 

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