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Observer app076
Registered: ‎01-29-2014

Does Vivado 2016.4 support VHDL-2008 Alias?


I am stuck with using Vivado 2016.4 for design & verification and a VHDL toplevel testbench. It appears that I cannot use the VHDL-2008 alias feature to probe internal signals because I get syntax errors with xvhdl. I tried googling but I see conflicting information on whether this is possible or not.

So my questions are

1) Is this supported in 2016.4?

2) If it is not supported, what alternative way do I have to access internal signals from the VHDL toplevel testbench?

3) Is the only way to do this to construct a Verilog toplevel testbench?


Here are the various ways I tried it - None of them worked!



alias_signal <= <<signal .tb.dut.signal : std_logic>>;

end block ALIASING;


ALIASING: process begin

alias_signal <= <<signal .tb.dut.signal : std_logic>>;

end process ALIASING;


Tried to put in global package file:

signal alias_signal : std_logic := .tb.dut.signal;

alias alias_signal is <<signal .tb.dut.signal : std_logic>>;



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3 Replies
Scholar richardhead
Registered: ‎08-01-2012

Re: Does Vivado 2016.4 support VHDL-2008 Alias?

First things first - Alias is not a 2008 feature. Alias is something that has been in VHDL since the beginning. The feature you are talking about is external names. It can be conveniant to use an alias to an external name to reduce the typing required.

According to the UG900, external names are supported, but I dont know for 2016.4, why cant you use the latest 2018.3?

You also have the syntax incorrect for the alias. For an alias to an external name:

alias your_alias is << (class) my_external_path : (type) >>;

where (class) = signal/variable/constant and (type) is the type of the object.

so, for example, lets assume you have a signal called some_sig thats an 8 bit slv inside an instatiattion called inst1

alias internal_sig is << signal inst1.some_sig : std_logic_vector(7 downto 0) >>;

This alias can be declared in any declarative region (ie. before any "begin"). But remember that code order is important - the alias must be declared after inst1 is instantiated, otherwise it cannot see it. So putting it in a global package is not going to work as it wont be able to see inst1.

And while verilog does have heirarchical references, they do not generally work across Verilog/VHDL code boundaries.

So post the code - maybe it can be fixed.

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Observer app076
Registered: ‎01-29-2014

Re: Does Vivado 2016.4 support VHDL-2008 Alias?

Thanks but I still don't understand what the actual answer is :). The same construct works in Vivado 2017.1 so I think the syntax is correct but may be 2016.4 has a different style of doing it. Let me know. I cannot switch Vivado versions because our whole project release structure is highly rigid and any tool version change is not allowed without a whole validation process. (the stick with what works program :) )

Here is a snippet of my code (Top_tb)


Architecture HW of Top_tb is
signal pwrup_seq_done : std_logic;
Begin uut: ENTITY work.Top PORT MAP ( -- signals ); ALIASING: BLOCK BEGIN pwrup_seq_done <= <<signal .Top_tb.uut.PwrUpSeq_done : STD_LOGIC>>; END BLOCK ALIASING;
End HW;


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Scholar richardhead
Registered: ‎08-01-2012

Re: Does Vivado 2016.4 support VHDL-2008 Alias?

This is not an alias,  this is assigning a local signal from an external name.  If it works in 2017.1 but not 2016.4, then I guess that is not supported in 2016.4.

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