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Highlighted
302 Views
Registered: ‎10-22-2020

Does Vivado simulator in 2020.1 support tracing variables

I have a very simple simulation and cannot see variables from my top level test bench, even though enabled in the GUI!  Is this not supported?

process(clk)
    variable count1: integer := 0;
    variable count2: integer := 0;
begin
   if rising_edge(clk)then
       if (count1 < 10) then
           count1 := count1 + 1;
           reset <= '0';
     elsif (count2 < 10) then
         count2 := count2 + 1;
         reset <= '1';
    else
        reset <= '0';
    end if;
end if;
end process;

 

pgigliotti_usac_1-1604963027496.png

 

 

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6 Replies
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Xilinx Employee
Xilinx Employee
221 Views
Registered: ‎05-01-2019

Hi,

It is supported. Please select 'VHDL Process' from scope window.

harikade_0-1605517466577.png

 

Thanks,

Harika.

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Highlighted
Visitor
Visitor
193 Views
Registered: ‎11-17-2020

Hi,

Is it also possible to display a VHDL variable in the waveform window? When I right-click a variable, the "Add to waveform window" option is greyed out. For signals, it works fine.

Thanks.

Variable.png
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Xilinx Employee
Xilinx Employee
175 Views
Registered: ‎05-01-2019

Hi,

Vivado Simulator does not yet support tracing of VHDL variables.

Thanks,

Harika.

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Highlighted
148 Views
Registered: ‎10-22-2020

No it doesn't. The add to wave for is greyed out when you select it. This is really lame. Is it expected to support this in the future? What is the best workaround - buy a 3rd party tool?
Highlighted
Teacher
Teacher
142 Views
Registered: ‎07-09-2009

welcome to the world of Xilinx lack of support for VHDL .

This has been asked for many years
but the ears dont seem to hear.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Highlighted
Scholar
Scholar
107 Views
Registered: ‎08-01-2012

Its not like all other simulators have had this ability for years
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