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Observer hse07013
Observer
5,206 Views
Registered: ‎09-20-2011

EDK Kintex6 PCI Express simulation error

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Hello,

 

I want to simulate my EDK design in modelsim. Unfortunately, my efforts are without success. Modelsim always ends with "# Error loading design".

I compiled all libraries in EDK (Compile Simulation Libraries...) for Virtex6, Virtex7 and Kintex7, with Verilog and VHDL option enabled. 

 

Modelsim 10.0 console output:

# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_pcie(structure)
# Loading axi_enhanced_pcie_v1_02_a.enhanced_core_top_wrap
# Loading axi_enhanced_pcie_v1_02_a.axi_pcie_enhanced_core_top
# Loading axi_enhanced_pcie_v1_02_a.pcie_7x_v1_3
# Loading axi_enhanced_pcie_v1_02_a.pcie_7x_v1_3_pcie_top
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_top
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_rx
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_rx_pipeline
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_rx_destraddler
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_rx_null_gen
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_rx_demux
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_tx
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_tx_port_mux
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_tx_pipeline
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_tx_arbiter
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_cfg
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_cfg_slave
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_cfg_gen_sink
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_cfg_block_bridge
# Loading axi_enhanced_pcie_v1_02_a.axi_enhanced_cfg_event_handler
# Loading axi_enhanced_pcie_v1_02_a.axi_lite_ipif
# Loading axi_enhanced_pcie_v1_02_a.slave_attachment
# Loading axi_enhanced_pcie_v1_02_a.address_decoder
# Loading axi_enhanced_pcie_v1_02_a.pcie_7x_v1_3_pcie_7x
# Loading axi_enhanced_pcie_v1_02_a.pcie_7x_v1_3_pcie_bram_top_7x
# Loading axi_enhanced_pcie_v1_02_a.pcie_7x_v1_3_pcie_brams_7x
# Loading unisims_ver.PCIE_2_1
# Loading axi_enhanced_pcie_v1_02_a.pcie_7x_v1_3_pcie_pipe_pipeline
# Loading axi_enhanced_pcie_v1_02_a.pcie_7x_v1_3_pcie_pipe_misc
# Loading axi_enhanced_pcie_v1_02_a.pcie_7x_v1_3_pcie_pipe_lane
# Loading axi_enhanced_pcie_v1_02_a.pselect_f
# Loading axi_enhanced_pcie_v1_02_a.pcie_7x_v1_3_pcie_bram_7x
# Loading axi_enhanced_pcie_v1_02_a.pcie_7x_v1_3_gt_top_ies
# Loading axi_enhanced_pcie_v1_02_a.pcie_7x_v1_3_pipe_wrapper_ies
# Loading axi_enhanced_pcie_v1_02_a.pcie_7x_v1_3_pipe_reset
# ** Error: (vsim-3033) /opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_enhanced_pcie_v1_02_a/hdl/verilog/pcie_7x_v1_3_pcie_bram_7x.v(206): Instantiation of 'BRAM_TDP_MACRO' failed. The design unit was not found.
#         Region: /system/PCI_Express/PCI_Express/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/genblk1/k7_pcie_7x_v1_3_inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0]/ram/use_tdp
#         Searched libraries:
#             /home/bernhard/xilinx_sim/xilinxcorelib_ver
#             /home/bernhard/xilinx_sim/secureip
#             /home/bernhard/xilinx_sim/unisims_ver
#             /home/bernhard/xilinx_sim/edk/axi_enhanced_pcie_v1_02_a

 

RAMB36 in unisims_ver library:

module RAMB36 (CASCADEOUTLATA, CASCADEOUTLATB, CASCADEOUTREGA, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB,
	       ADDRA, ADDRB, CASCADEINLATA, CASCADEINLATB, CASCADEINREGA, CASCADEINREGB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB);

...

    output CASCADEOUTLATA, CASCADEOUTREGA;
    output CASCADEOUTLATB, CASCADEOUTREGB;
    output [31:0] DOA;
    output [31:0] DOB;
    output [3:0] DOPA;
    output [3:0] DOPB;
    
    input ENA, CLKA, SSRA, CASCADEINLATA, CASCADEINREGA, REGCEA;
    input ENB, CLKB, SSRB, CASCADEINLATB, CASCADEINREGB, REGCEB;
    input [15:0] ADDRA;
    input [15:0] ADDRB;
    input [31:0] DIA;
    input [31:0] DIB;
    input [3:0] DIPA;
    input [3:0] DIPB;
    input [3:0] WEA;
    input [3:0] WEB;
...

The position where the instantiation takes place:

pcie_7x_v1_3_pcie_bram_7x.v(206)

 

        BRAM_TDP_MACRO #(
               .DEVICE        (DEVICE),
               .BRAM_SIZE     (BRAM_SIZE),
               .DOA_REG       (0),
               .DOB_REG       (DOB_REG),
               .READ_WIDTH_A  (WIDTH),
               .READ_WIDTH_B  (WIDTH),
               .WRITE_WIDTH_A (WIDTH),
               .WRITE_WIDTH_B (WIDTH),
               .WRITE_MODE_A  (WRITE_MODE)
               )
        RAMB36(
               .DOA            (),
               .DOB            (rdata_o[WIDTH-1:0]),
               .ADDRA          (waddr_i[ADDR_MSB:0]),
               .ADDRB          (raddr_i[ADDR_MSB:0]),
               .CLKA           (user_clk_i),
               .CLKB           (user_clk_i),
               .DIA            (wdata_i[WIDTH-1:0]),
               .DIB            ({WIDTH{1'b0}}),
               .ENA            (wen_i),
               .ENB            (ren_i),
               .REGCEA         (1'b0),
               .REGCEB         (rce_i),
               .RSTA           (reset_i),
               .RSTB           (reset_i),
               .WEA            ({WE_WIDTH{1'b1}}),
               .WEB            ({WE_WIDTH{1'b0}})
               );

 Hopefully anybody can help!

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Accepted Solutions
Xilinx Employee
Xilinx Employee
6,566 Views
Registered: ‎07-16-2008

Re: EDK Kintex6 PCI Express simulation error

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You need to map and reference library 'unimacro_ver' instead of 'unimacro'.

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Observer hse07013
Observer
5,205 Views
Registered: ‎09-20-2011

Re: EDK Kintex6 PCI Express simulation error

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Sorry, here is the EDK MHS-file!

-----------------------------------------------------------------------------------------
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Xilinx Employee
Xilinx Employee
5,193 Views
Registered: ‎07-16-2008

Re: EDK Kintex6 PCI Express simulation error

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It looks you didn't compile unimacro library.

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Observer hse07013
Observer
5,188 Views
Registered: ‎09-20-2011

Re: EDK Kintex6 PCI Express simulation error

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Thanks,

 

I thought that the EDK would include all libraries for me.

 

I added the following line to the system.do file:

vmap unimacro "/home/bernhard/xilinx_sim/unimacro/"

 

I changed the system_setup.do file:

alias c   "do system.do; set xcmdc 1"
alias s   "vsim -novopt -t ps -L unimacro -L xilinxcorelib_ver -L secureip -L unisims_ver +notimingchecks system glbl; set xcmds 1"

 But now I get another error:

# Loading unimacro.bram_tdp_macro(bram_v)
# ** Fatal: (vsim-3346) Output port 'DOA' is not constrained.
#    Time: 0 ps  Iteration: 0  Instance: /system/PCI_Express/PCI_Express/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/genblk1/k7_pcie_7x_v1_3_inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0]/ram/use_tdp/ramb36 File: /opt/Xilinx/13.4/ISE_DS/ISE/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd Line: 200
# FATAL ERROR while loading design
# Error loading design

 I have no idea, how to solve this. It seems the simulator has problems with not having defined the width of the vector.

port (
    DOA : out std_logic_vector;
    DOB : out std_logic_vector;

 

Thanks for your solution(s)

-----------------------------------------------------------------------------------------
It's always good practice giving feedback, when description/solution/recommendation have been helpful!
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Xilinx Employee
Xilinx Employee
6,567 Views
Registered: ‎07-16-2008

Re: EDK Kintex6 PCI Express simulation error

Jump to solution

You need to map and reference library 'unimacro_ver' instead of 'unimacro'.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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Observer hse07013
Observer
5,182 Views
Registered: ‎09-20-2011

Re: EDK Kintex6 PCI Express simulation error

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Thank you, your solution switching to the unimacro verilog library (unimacro_ver) works!

-----------------------------------------------------------------------------------------
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