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Newbie ahayes
Newbie
171 Views
Registered: ‎04-04-2019

ERROR: [XSIM 43-3217] - Incorrect project file syntax... even with a library selected

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I'm trying to simulate a vhdl project as packaged IP, but I'm running into the following error: (confidential info replaced with "...")

INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/.../source/Workspaces/.../.../.../SW/.../hw/xzynq_hw/....tmp/.../...sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_apb_xmit_vhdl.prj"
ERROR: [XSIM 43-3255] File name is missing.
ERROR: [XSIM 43-3217] tb_apb_xmit_vhdl.prj (line 3): Incorrect project file syntax. Correct syntax is one of: vhdl <worklib> <file>, verilog <worklib> <file> [<file> ...] [[-d <macro>] ...] [[-i <include>] ...], or NOSORT. Presence of NOSORT on a line of its own disables file order sorting.
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

The first few lines of the .prj file are as follows: (project name replaced with "...")

# compile vhdl design source files
vhdl xil_defaultlib \
"../../../../../../../ip_repo/.../src/auto_ptrt.vhd" \
"../../../../../../../ip_repo/.../src/gm_pkg.vhd" \
"../../../../../../../ip_repo/.../src/pk_pkg.vhd" \
"../../../../../../../ip_repo/.../src/clk.vhd" \

I referenced this solution, however the problem persists even though all files have a project selected.

Is there anything else that would cause this error? Anything else I should try?

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Newbie ahayes
Newbie
142 Views
Registered: ‎04-04-2019

Re: ERROR: [XSIM 43-3217] - Incorrect project file syntax... even with a library selected

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Solved - the "line 3" was just a misdirection

For anyone who has this issue in the future, your .prj file should specify a library like this:

vhdl xil_defaultlib  \

If it's blank like this, it will throw errors - go through and assign a library to each file below this:

vhdl   \

 

 

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Newbie ahayes
Newbie
143 Views
Registered: ‎04-04-2019

Re: ERROR: [XSIM 43-3217] - Incorrect project file syntax... even with a library selected

Jump to solution

Solved - the "line 3" was just a misdirection

For anyone who has this issue in the future, your .prj file should specify a library like this:

vhdl xil_defaultlib  \

If it's blank like this, it will throw errors - go through and assign a library to each file below this:

vhdl   \

 

 

View solution in original post

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