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Visitor i_ilias
Visitor
2,549 Views
Registered: ‎06-26-2018

ERROR: [XSIM 43-3268] Simulating a custon IP with AXI4-Lite interface

Hi All,

I'm using vivado 2018.3 and I created a custom IP withe the IP manager. 

When i try to launch my simulation I have this error:

INFO: [Vivado 12-5682] Launching behavioral simulation in 'z:/developement/vhdl/ip_repo/edit_axi_pwm_v1_0.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Tb_Pwm' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'z:/developement/vhdl/ip_repo/edit_axi_pwm_v1_0.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Tb_Pwm_vhdl.prj"
ERROR: [XSIM 43-3268] Logical library name '"../../../../axi_pwm_1.0/hdl/axi_pwm_v1_0.vhd"' should not contain white space, new line, /, \, = or .
ERROR: [XSIM 43-3217] Tb_Pwm_vhdl.prj (line 3): Incorrect project file syntax. Correct syntax is one of: vhdl <worklib> <file>, verilog <worklib> <file> [<file> ...] [[-d <macro>] ...] [[-i <include>] ...], or NOSORT. Presence of NOSORT on a line of its own disables file order sorting.
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'Z:/developement/VHDL/ip_repo/edit_axi_pwm_v1_0.sim/sim_1/behav/xsim/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'Z:/developement/VHDL/ip_repo/edit_axi_pwm_v1_0.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
ipx::merge_project_changes files [ipx::current_core]
WARNING: [IP_Flow 19-5226] Project source file 'z:/developement/VHDL/ip_repo/axi_pwm_1.0/component.xml' ignored by IP packager.

 

I just don't understand why it complains about the syntax of the files names...

 

Thanks!

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11 Replies
Visitor i_ilias
Visitor
2,517 Views
Registered: ‎06-26-2018

Re: ERROR: [XSIM 43-3268] Simulating a custon IP with AXI4-Lite interface

It seems to be an error from 2018.3 update...

it works with vivado 2017.4

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Moderator
Moderator
2,495 Views
Registered: ‎09-15-2016

Re: ERROR: [XSIM 43-3268] Simulating a custon IP with AXI4-Lite interface

Hi @i_ilias,

Can you please share the archived project to check this issue at our end.

 

 

Thanks & Regards,
Sravanthi B
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Visitor i_ilias
Visitor
2,492 Views
Registered: ‎06-26-2018

Re: ERROR: [XSIM 43-3268] Simulating a custon IP with AXI4-Lite interface

Hi,

I switched back for 2017.4 version so it's a 2017 project.

But here is what I did on 2018:

- create my IP

- New project

- New Block Design

- instert custom IP 

- Edit IP

- create a tb for it

- launch

- ERROR

 

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Newbie neverender
Newbie
2,442 Views
Registered: ‎12-14-2018

Re: ERROR: [XSIM 43-3268] Simulating a custon IP with AXI4-Lite interface

I just ran into the same problem. I noticed a couple of potential issues with the generated .prj passed to xvhdl:

# compile vhdl design source files
vhdl   \
"../../../../omw_test_1.0/hdl/omw_test_v1_0_S_AXI.vhd" \
"../../../../omw_test_1.0/hdl/omw_test_v1_0.vhd" \

# Do not sort compile order
nosort

1) There are three consecutive spaces immediately following the vhdl directive, where the work library argument should seemingly appear.
2) UG900 specifies that only a single source file can be passed per line with the vhdl directive (as opposed to the verilog directive).

I tried fixing up the .prj file manually, but since it gets automatically regenerated and overwritten every time you hit the "Run Simulation" action, it didn't help.

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Newbie neverender
Newbie
2,429 Views
Registered: ‎12-14-2018

Re: ERROR: [XSIM 43-3268] Simulating a custon IP with AXI4-Lite interface

Update: Editing the "LIBRARY" property for the .vhd sources, and changing it from its default of blank/empty, resolved this issue for me.

Observer andycap
Observer
2,422 Views
Registered: ‎09-18-2017

Re: ERROR: [XSIM 43-3268] Simulating a custon IP with AXI4-Lite interface

Thanks for the tip on setting the library property, this worked for me as well.

 

Andy

Newbie jsusongc4s
Newbie
2,199 Views
Registered: ‎05-18-2018

Re: ERROR: [XSIM 43-3268] Simulating a custon IP with AXI4-Lite interface

Very helpful! Sometimes pictures help, attached are example before and after screenshots. The library field needs to be updated on all source files before running simulation.
Screenshot from 2019-01-22 11-51-21.png
Screenshot from 2019-01-22 11-52-52.png
Observer mgaiser
Observer
1,825 Views
Registered: ‎07-23-2013

Re: ERROR: [XSIM 43-3268] Simulating a custon IP with AXI4-Lite interface

It seems to be necessary to apply this setting each time the project is re-opened in IP Packager.

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Contributor
Contributor
973 Views
Registered: ‎04-01-2019

Re: ERROR: [XSIM 43-3268] Simulating a custon IP with AXI4-Lite interface

Very helpful and also fixed this annoying bug. Xilinx please fix.

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Visitor azimir58
Visitor
759 Views
Registered: ‎10-31-2018

Re: ERROR: [XSIM 43-3268] Simulating a custon IP with AXI4-Lite interface

Thanks for the library hint. I my case I changed it from blank to xil_defaultlib and it did the trick.

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Participant adityadhananjay
Participant
45 Views
Registered: ‎04-28-2017

Re: ERROR: [XSIM 43-3268] Simulating a custon IP with AXI4-Lite interface

Thank you very much. This worked for me too. In my case, I also had change to "xil_defaultlib" for all nested verilog source files.

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