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pgigliotti_usac
Explorer
Explorer
520 Views
Registered: ‎10-22-2020

ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

I am using Vivado 2020.1 tools to simulate my design.  All source files are of type VHDL-2008.

I am trying to look at a lower level signal to gate activities in my top level testbench.

I have added the following alias, signals and code, which causes the above error message

alias Data_from_CTL_empty is <<signal Inst_VMUX_Top.Inst_Switch_IF.Data_from_CTL_empty : std_logic>>;

signal SW_from_CTL_empty_rising: boolean;
signal Clear_Data_from_CTL_empty : boolean;

process(sys_reset, Data_from_CTL_empty, Clear_Data_from_CTL_empty);begin
    if(sys_reset = '1') then
          SW_from_CTL_empty_rising <= false;
    elsif(rising_edge(Data_from_CTL_empty)) then
          SW_from_CTL_empty_rising <= true;
    elsif(Clear_Data_from_CTL_empty = true)then
         SW_from_CTL_empty_rising <= false;
     end if;
end process;

Any toought (other than move to questa).

 

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4 Replies
richardhead
Scholar
Scholar
501 Views
Registered: ‎08-01-2012

Without the full code so the problem can be re-created, it will be very difficult to comment.

But I would recommend a move to questa even without the crash.

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pgigliotti_usac
Explorer
Explorer
449 Views
Registered: ‎10-22-2020

Well, if I remove everything but the alias. It runs without issue.  Yes, this Vivado simulator is not all that great.  One thing that I really dislike is that it cannot display variables in the waveform viewer.  I have lost numerous hours going back into my code adding debug signals, since I cannot track the value of variables. A serious short-coming of this tool.

Regarding Questa, we are in the process working with our IT department to get it installed. Another pain in my life.

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pgigliotti_usac
Explorer
Explorer
449 Views
Registered: ‎10-22-2020

BTW, I was a Xilinx FAE a while back and we used to keep a cube in San Jose  open for FAEs, and it had a name plate Richard Cranium on the wall. Just saying.

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bandi
Moderator
Moderator
340 Views
Registered: ‎09-15-2016

Hi @pgigliotti_usac ,

Can you please share a test case to reproduce and check this issue at our end.

Thanks & Regards,
Sravanthi B
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