10-23-2019 12:35 AM
10-23-2019 05:11 AM
Dont expect it anytime soon.
The synth engine currently has better VHDL 2008 support than simulation. (see UG900 compared to 901).
What are you trying to force and release? usually they are only used for fault injection. do you really need to do this?
10-23-2019 05:48 AM
Thanks for taking a look. Yes, I would like to use this feature of VHDL2008 for fault injection. Of course coding in VHDL was still possible before VHDL2008, but force and release are useful and also make my testbench cross platform compatible with modelsim, which does support them. Here's the code
signal tx_rx : std_logic; --- tx_rx is an output from DUT_TX and an input to DUT_RX -- in the testbench process tx_rx <= force '0'; -- some tests tx_rx <= release;
Am I missing an easier way?
I'd still be interested to get a comment from Xilinx about their plans for supporting these keywords. I's not like Xilinx isn't releasing new versions of Vivado regularly, so the opportunity is there. Paying customers and the community all need good testbenches, so it would not be a waste of effort.
10-24-2019 03:39 AM - edited 10-24-2019 03:39 AM
Dont know another way around. Have you tried force/release in verilog? That has been around much longer.
It also seems possible from tcl "add_force" command.
But obviously not yet from 2008.
Good luck with testing.
If you have access to Modelsim, I would just not bother with Xilinx simulator.
10-26-2019 03:21 PM
Hello - I there are many Xlinx moderators on the board. Do you have any information about plans to support VHDL2008 force and release in the simulator?