12-10-2018 03:34 AM
I'm simulating a project which is made of some VHDL and some Verilog based blocks. The top module and test bench are in VHDL.
The simulation is working correct until I duplicate a module with correct signals in my top module. The point is that I am sure this module is working correct, because I have another one of this module in my design. But when the second one is added the simulation does not start at all and I see the following error in TCL console:
ERROR signal EXCEPTION_ACCESS_VIOLATION received
I have tried a lot of suggested workarounds, but no one helped. For example rechecking the syntaxes, writing the test bench and top module in Verilog language instead of VHDL, moving the project to another version of Vivado and so on... Really I do not know what to do any more!
P.S: Vivado version is 2017.4.1, but I made the project in Vivado 2015.4 and the same problem occurs. My OS is Windows 10 - 64 bit.
Any help is highly appreciated.
12-10-2018 03:59 AM
I'm sorry I can't publish the design files because of the company rules. The point is that I am sure there is no errors in my design.
For example assume that I have a module in my design which is named "A" and the simulation is working well. If I instantiate another "A" module with a different port mapping, the error occurs and I can't simulate any more.