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Visitor adanowitz
Visitor
7,777 Views
Registered: ‎02-18-2015

EXCEPTION_ACCESS_VIOLATION Vivado 2014.4 when flattening hierarchy

I'm running Vivado 2014.4 through the GUI on a Windows 8.1 machine with 8 GB of RAM. If I run synthesis on my design with the -flatten_hierarchy setting set to either "full" or "rebuilt," I get an EXCEPTION_ACCESS_VIOLATION when trying to synthesize a vga driver block posted below. If I comment out the vga_clk, synthesis completes. Conversely, if I turn flatten_hierarchy to "off," I can get through synthesis and implementation with no errors.

 

-- 
-- The interface to the VGA driver module. Extended to both read and write
-- to the framebuffer (to check the color values of a particular pixel).
--
-- Original author: unknown
-- 
-- Modified by: <redacted>
-- CPE233, Winter 2012, CalPoly
--



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity vgaDriverBuffer is
    Port (         CLK, we : in std_logic;
                   wa : in std_logic_vector (10 downto 0);
                   wd : in std_logic_vector (7 downto 0);
                   Rout : out std_logic_vector(2 downto 0);
                   Gout : out std_logic_vector(2 downto 0);
                   Bout : out std_logic_vector(1 downto 0);
                   HS      : out std_logic;
                   VS      : out std_logic;
                   pixelData &colon; out std_logic_vector(7 downto 0)
              );
end vgaDriverBuffer;

architecture Behavioral of vgaDriverBuffer is

-- vga driver signals
signal rgbout : std_logic_vector(7 downto 0);
signal ra : std_logic_vector(10 downto 0);
signal vgaData &colon; std_logic_vector(7 downto 0);
signal fb_wr, vgaclk : std_logic;
signal red, green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(1 downto 0);
signal row, column         : std_logic_vector(9 downto 0);

-- Added to read the pixel data at address 'wa' -- pfh, 3/1/2012
signal pixelVal : std_logic_vector(7 downto 0);


   -- Declare VGA driver components
component VGAdrive is

  port( clock              : in std_logic;  -- 25.175 Mhz clock
        red, green         : in std_logic_vector(2 downto 0);
        blue               : in std_logic_vector(1 downto 0);
        row, column        : out std_logic_vector(9 downto 0); -- for current pixel
        Rout, Gout         : out std_logic_vector(2 downto 0);
        Bout               : out std_logic_vector(1 downto 0);
        H, V : out std_logic); -- VGA drive signals
end component;

component ram2k_8 is
  port(clk:           in  STD_LOGIC;
       we:            in  STD_LOGIC;
       ra, wa:        in  STD_LOGIC_VECTOR(10 downto 0);
       wd:            in  STD_LOGIC_VECTOR(7 downto 0);
       rd:            out STD_LOGIC_VECTOR(7 downto 0);
       pixelVal:      out STD_LOGIC_VECTOR(7 downto 0));
end component; 

component vga_clk_div is
  port(clk     : in std_logic;
       clkout  : out std_logic);
end component;


begin


frameBuffer : ram2k_8      port map (  clk => clk,       --CLK
                                       we => we,
                                       ra => ra,
                                       wa => wa,
                                       wd => wd,
                                       rd => vgaData,
                                       pixelVal => pixelVal);
                                       
vga_out : VGAdrive         port map (  clock => vgaclk,
                                       red => red,
                                       green => green,
                                       blue => blue,
                                       row => row,
                                       column => column,
                                       Rout => Rout,
                                       Gout => Gout,
                                       Bout => Bout,
                                       H => HS,
                                       V => VS     );                                     
                                       
 -- read signals from fb
   ra <= row (8 downto 4) & column(9 downto 4); 
   red <= vgaData(7 downto 5);      
   green <= vgaData(4 downto 2);
   blue <= vgaData(1 downto 0);
   pixelData <= pixelVal; -- returns the pixel data in the framebuffer at address 'wa'

   

    vga_clk  : vga_clk_div  port map (  clk => CLK, clkout => vgaclk);


end Behavioral;

 

-- 
-- Declares a clock divider to synchronize the VGA scanlines
--
-- Original author: unknown
--
-- <redacted>
-- CPE233, Winter 2012, CalPoly
--


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity vga_clk_div is
  port(clk         : in std_logic;
         clkout     : out std_logic);
end vga_clk_div;

architecture Behavioral of vga_clk_div is

signal tmp_clkf : std_logic;

begin

   my_div_fast: process (clk,tmp_clkf)              
      variable div_cnt : integer := 0;   
   begin
      if (rising_edge(clk)) then   
         if (div_cnt = 0) then
            tmp_clkf <= not tmp_clkf;
            div_cnt := 0;
         else
            div_cnt := div_cnt + 1;
         end if;
      end if;
      clkout <= tmp_clkf;
   end process my_div_fast;    
    
end Behavioral;

 

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2 Replies
Scholar austin
Scholar
7,772 Views
Registered: ‎02-27-2008

Re: EXCEPTION_ACCESS_VIOLATION Vivado 2014.4 when flattening hierarchy

a,

 

When you specify a memory in your design (the way you have) it might not be synthesized by using the FPGA device's BRAM.  Not sure if this is getting in your way, but the memories should get replaced by BRAM instantiations.  In ASIC development, wrappers are used to target such memories to BRAM for verification of the RTL prior to synthesis, place, and route of the ASIC.

 

I have seen the case where individual DFF are used to create the RAM....

 

Look at all the reports.  When the exception occurs, there must be some complaints or evidence prior posted in the reports to let you know something is going wrong.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
7,753 Views
Registered: ‎07-01-2010

Re: EXCEPTION_ACCESS_VIOLATION Vivado 2014.4 when flattening hierarchy

Do you see any issue while synthesizing individual modules (ram2k_8 , VGAdrive )?
If you are able to synthesize these modules individually then you have to look at the interface between ram2k_8 and VGAdrive.

Can you try commenting the below 3 lines and see if the design synthesize?
red <= vgaData(7 downto 5);
green <= vgaData(4 downto 2);
blue <= vgaData(1 downto 0);


Regards,
Achutha
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