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Anonymous
Not applicable
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Editing a testbench file

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How do I edit the testbench vhw file. I made a waveform for test vhdl code and I want to use the vhw code to write the results into a text file. The vhw generated by xilinx declares the results.txt file but does not make use of it.

how do I change it.

Also any tutorials on writing test benches?

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edv
Xilinx Employee
Xilinx Employee
11,988 Views
Registered: ‎08-15-2007

Sure!  The .vhw is a general VHDL test bench.  It can be used in any HDL simulator. 

 

 

Eddie

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edv
Xilinx Employee
Xilinx Employee
10,152 Views
Registered: ‎08-15-2007

Hello,

 

VHW files are generated as read-only.  If you need to modify it, either change the permissions on the file, or perform a "Save As" in order to save the file as .vhd instead of .vhw.  You'll then be able to modify the file as any other source file.

 

Refer to the following Xilinx Application Note for creating test benches:

 

XAPP199: Writing Efficient Testbenches

 

Hope this helps.

Eddie
Anonymous
Not applicable
10,139 Views

Thanks.

Can I run the teshbench on modelsim?

 

I am testing a vhd file with a testbench thats also vhd. Will running the testbench vhd, result in simulation?

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edv
Xilinx Employee
Xilinx Employee
11,989 Views
Registered: ‎08-15-2007

Sure!  The .vhw is a general VHDL test bench.  It can be used in any HDL simulator. 

 

 

Eddie

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Anonymous
Not applicable
10,106 Views

One more question - is there a tutorial/app note on writing the test results to files?

The vhw files from the waveform do contain results.txt declaration, but they don't contain the code to write to txt file.

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edv
Xilinx Employee
Xilinx Employee
10,100 Views
Registered: ‎08-15-2007

In VHDL, you can use the  "File" type to declare input and output "file" variables, pointing to disk files.  Check out the following link for a general example.

 

In Verilog, you can use the $fwrite system task to write out to a file.  A google search on "fwrite verilog syntax" should yield you a lot of internet literature on the use of this system task.


 

Hope this helps.

Message Edited by edv on 03-12-2009 05:41 PM
Eddie
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Anonymous
Not applicable
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I got that part. I need help formatting-

 

I have 3 variables - clk, din, dout

How do I write them to a file one next to other, with lables in the first line - clk   din   dout

I can't write more than one variable to a line variable.

 

This is what I have now and it writes one after the other. 

 

                     write(L1, linenumber, right, 2);                     
                     WRITE(L1, clk, right, 2);
                     write(L2, din, right, 2);
                     write(L3, dout,right, 2);
                     writeline(results, L1);
                     writeline(results, L2);
                     writeline(results, L3);
                     linenumber<=linenumber+1;

 

 

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edv
Xilinx Employee
Xilinx Employee
10,093 Views
Registered: ‎08-15-2007

Instead of "writeline", can you not just use "write" so you can continually append the variable values? 

 

I haven't used write / writeline much more than just to write a variable to a text file, but it's worth a try.

Eddie
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Anonymous
Not applicable
10,077 Views

Now I have a new problem-

When I run the testbench, the waveform and the result.txt output do not match. The result file is one clock cycle delayed. 

In the waveform,  dout goes high after 4 clock cycles after din. But in the results file, it goes high after 5 clock cycles.

This is a 4 bit falling edge shift register. 

 

I am writing to the results file on falling edge of clock in a process.

The results file is like below -

Line#, CLK, din, dout

1    0     1       U
2    0     0       0
3    0     0       0
4    0     0       0
5    0     0       0
6    0     0       1
7    0     0       0

 

 

tbw1.PNG
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